JAJSLV7A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RRG|40
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage;  ID(hs) = DH to SW current;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤ TJ ≤ 125 °C; 10 ≤ VAUX ≤ 26; 7.5 ≤ VBST_SW ≤ 26; VEN = 5 V; VINL = 0 V; VINH = 0 V; RRDRVL = 0 Ω; RRDRVH_SW = 0 Ω; RCS = 100 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
td(on)(Idrain)(ls) Drain current turn-on delay time From VINL > VINL,IT+ to ID(ls) > 50 mA, VBUS = 400 V, LHB current  = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 68 ns
slew rate setting 1 40
slew rate setting 2 35
slew rate setting 3 (fastest) 34
td(on)(ls) Turn-on delay time From VINL > VINL,IT+ to VDS(ls) < 320 V, VBUS = 400 V, LHB current  = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 91 ns
slew rate setting 1 50
slew rate setting 2 43
slew rate setting 3 (fastest) 37
tr(on)(ls) Turn-on rise time From VDS(ls) < 320 V to VDS(ls) < 80 V, VBUS = 400 V, LHB current  = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 14.9 ns
slew rate setting 1 5.6
slew rate setting 2 3.8
slew rate setting 3 (fastest) 1.9
td(off)(ls) Turn-off delay time From VINL < VINL,IT– to VDS(ls) > 80 V, VBUS = 400 V, LHB current  = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 43 ns
tf(off)(ls) Turn-off fall time From VDS(ls) > 80 V to VDS(ls) > 320 V, VBUS = 400 V, LHB current  = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 12.5 ns
Turn-on slew rate From VDS(ls) < 250 V to VDS(ls) < 150 V, TJ = 25 ℃, VBUS = 400 V, LHB current  = 2 A, at below low-side slew rate settings,  see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 20 V/ns
slew rate setting 1 50
slew rate setting 2 70
slew rate setting 3 (fastest) 140
HIGH-SIDE GAN POWER FET
td(on)(Idrain)(hs) Drain current turn-on delay time From VINH > VINH,IT+ to ID(hs) > 50 mA, VBUS = 400 V, LHB current  = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 60 ns
slew rate setting 1 34
slew rate setting 2 31
slew rate setting 3 (fastest) 28
td(on)(hs) Turn-on delay time From VINH > VINH,IT+ to VDS(hs) < 320 V, VBUS = 400 V, LHB current  = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 86 ns
slew rate setting 1 46
slew rate setting 2 39
slew rate setting 3 (fastest) 32
tr(on)(hs) Turn-on rise time From VDS(hs) < 320 V to VDS(hs) < 80 V, VBUS = 400 V, LHB current  = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 13.1 ns
slew rate setting 1 4.7
slew rate setting 2 3.2
slew rate setting 3 (fastest) 1.7
td(off)(hs) Turn-off delay time From VINH < VINH,IT– to VDS(hs) > 80 V, VBUS = 400 V, LHB current  = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 37 ns
tf(off)(hs) Turn-off fall time From VDS(hs) > 80 V to VDS(hs) > 320 V, VBUS = 400 V, LHB current  = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 12.5 ns
Turn-on slew rate From VDS(hs) < 250 V to VDS(hs) < 150 V, TJ = 25 ℃, VBUS = 400 V, LHB current  = 2 A, at below high-side slew rate settings,  see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 20 V/ns
slew rate setting 1 65
slew rate setting 2 90
slew rate setting 3 (fastest) 165
CS
Settling time From ICS > 0.1*ICS(src)(final) to ICS < 0.9*ICS(src)(final), Low-side enabled into a 2 A load, 0 V ≤ VCS ≤ 2 V,  35 ns
EN
EN wake-up time VINL = 5 V, From VEN > VIT+ to ID(ls) > 10 mA 1 µs
BST
Start-up time from deep BST to SW discharge From VBST_SW ≥ VBST_SW,T+(UVLO) to high-side reacts to INH rising edge  with VBST_SW rising from 0 V to 10 V in 1 µs 5 µs
Start-up time from shallow BST to SW discharge From VBST_SW ≥ VBST_SW,T+(UVLO) to high-side reacts to INH rising edge  with VBST_SW rising from 5 V to 10 V in 0.5 µs 2 µs