SNOSDH5 November   2024 LMG2640

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Current-Sense Emulation
      3. 7.3.3  Bootstrap Diode Function
      4. 7.3.4  Input Control Pins (EN, INL, INH)
      5. 7.3.5  INL - INH Interlock
      6. 7.3.6  AUX Supply Pin
        1. 7.3.6.1 AUX Power-On Reset
        2. 7.3.6.2 AUX Under-Voltage Lockout (UVLO)
      7. 7.3.7  BST Supply Pin
        1. 7.3.7.1 BST Power-On Reset
        2. 7.3.7.2 BST Under-Voltage Lockout (UVLO)
      8. 7.3.8  Over-Current Protection
      9. 7.3.9  Over-Temperature Protection
      10. 7.3.10 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RRG|40
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発注情報

7.3.2 Current-Sense Emulation

The current-sense emulation function creates a scaled replica of the low-side GaN power FET positive drain current at the output of the CS pin. The current-sense emulation gain, GCSE, is 0.616mA output from the CS pin, ICS for every 1A passing into the drain of the low-side GaN power FET, ID.

Equation 1. GCSE = ICS / ID = 0.616mA / 1A = 0.000616

The CS pin is terminated with a resistor to AGND, RCS, to create the current-sense voltage input signal to the external power supply controller.

RCS is determined by solving for the traditional current-sense design resistance, RCS(trad), and multiplying by the inverse of GCSE. The traditional current-sense design creates the current-sense voltage, VCS(trad), by passing the low-side GaN power FET drain current, ID, through RCS(trad). The LMG2640 creates the current-sense voltage, VCS, by passing the CS pin output current, ICS, through RCS. The current-sense voltage must be the same for both designs.

Equation 2. VCS = ICS × RCS = VCS(trad) = ID × RCS(trad)
Equation 3. RCS = ID / ICS × RCS(trad) = 1 / GCSE × RCS(trad)
Equation 4. RCS = 1,623 × RCS(trad)

The CS pin is clamped internally to a typical 2.5V. The clamp protects vulnerable power-supply controller current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to become disconnected.

Figure 7-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the low-side GaN power-FET drain current while the low-side FET is enabled. The first cycle shows normal operation where the controller turns off the low-side GaN power FET when the controller current-sense input threshold is tripped. The second cycle shows a fault situation where the LMG2640 Overcurrent Protection turns off the low-side GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2640 avoids a hung controller INL pulse by generating a fast-ramping artificial current-sense emulation signal to trip the controller current-sense input threshold. The artificial signal persists until the INL pin goes to logic-low which indicates the controller is back in control of switch operation.


LMG2640 Current-Sense Emulation Operation

Figure 7-2 Current-Sense Emulation Operation