JAJSRX4 May   2024 LMG2650

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RFB|19
サーマルパッド・メカニカル・データ
発注情報

6.1 GaN Power FET Switching Parameters

Figure 6-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit is placed in the boost configuration to measure the low-side GaN switching parameters. The circuit is placed in the buck configuration to measure the high-side GaN switching parameters. The GaN FET not being measured in each configuration (high-side in the boost and low-side in the buck) acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode. Table 6-1 shows the details for each configuration.


LMG2650 GaN Power FET Switching Parameters Test Circuit

Figure 6-1 GaN Power FET Switching Parameters Test Circuit
Table 6-1 GaN Power FET Switching Parameters Test Circuit Configuration Details
CONFIGURATION GaN FET UNDER TEST GaN FET ACTING AS DIODE SBOOST SBUCK VINL VINH VGDH
Boost Low-side High-side Closed Open Double-pulse waveform 0V 0V
Buck High-side Low-side Open Closed 0V Double-pulse waveform 0V
Buck High-side Low-side Open Closed 0V 0V Double-pulse waveform

Figure 6-2 shows the GaN power FET switching parameters.

The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time td(on)(Idrain), turn-on delay time td(on), and turn-on rise time tr(on). Note that the turn-on rise time is the same as the VDS 80% to 20% fall time. All three turn-on timing components are a function of the RDRVx pin setting.

The GaN power FET turn-off transition has two timing components: turn-off delay time td(off), and turn-off fall time tf(off). Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are independent of the RDRVx pin setting, but heavily dependent on the LHB current.

The turn-on slew rate is measured over a turn-on rise time voltage delta (240V) to obtain a slew rate which is useful for EMI design. The RDRVx pin is used to program the slew rate.


LMG2650 GaN Power FET Switching Parameters

Figure 6-2 GaN Power FET Switching Parameters