The EN pin is referenced to AGND and is used to toggle the device between the active and standby modes described in the Device Functional Modes section.

The INL pin is referenced to AGND and is used to turn the low-side GaN power FET on and off.

The INH pin is referenced to AGND and is used to turn the high-side GaN power FET on and off. The INH pin is compatible with controllers that use a low-side referenced gate drive signal to control the high-side GaN power FET.

The GDH pin is referenced to SW and is used to turn the high-side GaN power FET on and off. The GDH pin is compatible with controllers that use a high-side referenced signal to control the high-side GaN power FET.

The LMG2650 is intended to be used with either the INH pin or the GDH pin controlling the high-side GaN power FET. Short the unused pin to its reference (INH to AGND or GDH to SW).

The input control pins have a typical 1V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400kΩ pull-down resistance to protect against floating inputs. The 400kΩ saturates for typical input voltages above 4V to limit the maximum input pull-down current to a typical 10uA. There are individual forward based ESD diodes from the EN, INL, and INH pins to the AUX pin. Avoid driving the EN, INL, and INH voltages higher than the AUX voltage. There is also a forward based ESD diode from the GDH pin to the BST pin. Avoid driving the GDH-to-SW voltage higher than the BST-to-SW voltage.

The INL turn-on action is blocked by the following conditions:

• Standby mode (as set by the EN pin above)
• INH in control of the INL/INH interlock
• AUX under-voltage lockout (UVLO)
• Low-side overtemperature protection
• Low-side GaN Power FET overcurrent protection

The INH turn-on action is blocked by the following conditions

• Standby mode (as set by the EN pin above)
• INL in control of the INL/INH interlock
• AUX UVLO
• Low-side overtemperature protection
• BST UVLO
• High-side overcurrent protection

The GDH turn-on action is blocked by the following conditions

• BST UVLO
• High-side overtemperature protection
• High-side overcurrent protection

Note that the INH pin is blocked by the low-side temperature protection while the GDH pin is blocked by the high-side temperature protection.

All the blocking conditions except the INL/INH interlock and the overcurrent protection act independently of the INL, INH, or GDH logic state. Figure 7-3 shows the operation of these control-input independent blocking conditions.

Figure 7-3 Control-Input-Independent Blocking Condition Operation

The INL/INH Interlock blocking action is described in the INL - INH Interlock section. Meanwhile, the overcurrent protection blocking action only asserts after the control input has turned on its respective GaN power FET. See the Overcurrent Protection section for the details.