JAJSRX4 May   2024 LMG2650

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are respect to AGND(1)
MIN MAX UNIT
VDS(ls) Low-side drain-source (SW to SL) voltage, FET off 650 V
VDS(surge)(ls) Low-side drain-source (SW to SL) voltage, surge condition, FET off (2) 720 V
VDS(tr)(surge)(ls) Low-side drain-source (SW to SL) transient ringing peak voltage, surge condition, FET off (2) 800 V
VDS(hs) High-side drain source (DH to SW) voltage, FET off 650 V
VDS(surge)(hs) High-side drain-source (DH to SW) voltage, surge condition, FET off (2) 720 V
VDS(tr)(surge)(hs) High-side drain-source (DH to SW) transient ringing peak voltage, surge condition, FET off (2) 800 V
Pin voltage to AGND AUX –0.3 30 V
EN, INL, INH –0.3 VAUX + 0.3 V
CS –0.3 5.5 V
RDRVL –0.3 4 V
Pin voltage to SW BST –0.3 30 V
RDRVH –0.3 4 V
GDH –0.3 VBST_SW + 0.3 V
ID(cnts)(ls) Low-side drain (SW to SL) continuous current, FET on –11.5 Internally limited A
ID(pulse)(oc)(ls) Low-side drain (SW to SL) pulsed current during overcurrent response time(3) 28 A
IS(cnts)(ls) Low-side source (SL to SW) continuous current, FET off 11.5 A
ID(cnts)(hs) High-side drain (DH to SW) continuous current, FET on –11.5 Internally limited A
ID(pulse)(oc)(hs) High-side drain (DH to SW) pulsed current during overcurrent response time(3) 28 A
IS(cnts)(hs) High-side source (SW to DH) continuous current, FET off 11.5 A
Positive sink current CS 10 mA
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –40 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) See GaN Power FET Switching Capability for more information on the GaN power FET switching capability.
(3) GaN power FET may self-limit below this value if it enters saturation.