JAJSSU3A January   2024  – July 2024 LMG3100R017

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Use With Analog Controllers
        5. 8.2.2.5 Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information

パッケージ・オプション

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発注情報

7.3.2 Start-up and UVLO

The LMG3100 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 7-1 VCC UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)HILISW
VCC - VSS < VCCR during device start-upHLHi-Z
VCC - VSS < VCCR during device start-upLHHi-Z
VCC - VSS < VCCR during device start-upHHHi-Z
VCC - VSS < VCCR during device start-upLLHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upHLHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upLHHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upHHHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upLLHi-Z
Table 7-2 VHB-HS UVLO Feature Logic Operation
CONDITION (VCC > VCCR for all cases below)HILISW
VHB-HS < VHBR during device start-upHLHi-Z
VHB-HS < VHBR during device start-upLHPGND
VHB-HS < VHBR during device start-upHHPGND
VHB-HS < VHBR during device start-upLLHi-Z
VHB-HS < VHBR - VHB(hyst) after device start-upHLHi-Z
VHB-HS < VHBR - VHB(hyst) after device start-upLHPGND
VHB-HS < VHBR - VHB(hyst) after device start-upHHPGND
VHB-HS < VHBR - VHB(hyst) after device start-upLLHi-Z