JAJSG97A September   2018  – March 2019 LMG3410R050 , LMG3411R050

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
      2.      100V/nsを超えるスイッチング性能
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 Over-current Protection
        2. 8.3.4.2 Over-Temperature Protection and UVLO
      5. 8.3.5 Drive Strength Adjustment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Paralleling GaN Devices
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

over operating free-air temperature range, 9.5 V < VDD < 18 V, VNEG = -14 V, VBUS = 400 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GaN FET
dv/dt Turn-on Drain Slew Rate RDRV = 15 kΩ 100 V/ns
RDRV = 40 kΩ 50
RDRV = 100 kΩ 25
Δdv/dt Slew Rate Variation Turn on, IL = 5 A, RDRV = 40 kΩ 25 %
dv/dt Edge Rate Immunity Drain dv/dt, device remains off inductor-fed, max di/dt = 10 A/ns 150 V/ns
fSW,GAN FET switching frequency 0.5 MHz
STARTUP
tSTART Startup Time, VIN rising above UVLO Time until gate responds to IN CNEG = 2.2 µF, CLDO = 1 µF 1 ms
DRIVER
tpd,on Propagation delay, turn on IN rising to IDS > 1 A, VDS = 400 V RDRV = 15 kΩ, VNEG = -14 V 18.5 ns
tdelay,on Turn on delay time IDS > 1 A to VDS < 320 V, ID = 5 A, RDRV = 15 kΩ 5.2 ns
tVDS,ft VDS fall time VDS = 320 V to VDS = 80 V, ID = 5 A, RDRV = 15 kΩ 2.9 ns
tpd,off Propagation delay, turn off IN falling to VDS > 10 V,ID = 5 A, RDRV = 15 kΩ 25.3 ns
tdelay,off Turn off delay time VDS = 10 V to VDS = 80 V, ID = 5 A, RDRV = 15 kΩ 8.9 ns
tVDS,rt VDS rise time VDS = 80 V to VDS = 320 V, ID = 5 A, RDRV = 15 kΩ 18 ns
FAULT
tcurr Current Fault Delay IDS > ITH to FAULT low 50 ns
tblank Current Fault Blanking Time VIN>VIH to end of blanking,  RDRV=15kΩ 55 ns
treset(1) Fault reset time IN held low 250 350 500 µs
(1) Note: the reset time applies to the thermal-shut-down on both devices and the latched OCP on the LMG3410R050.