JAJSG97A September   2018  – March 2019 LMG3410R050 , LMG3411R050

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
      2.      100V/nsを超えるスイッチング性能
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 Over-current Protection
        2. 8.3.4.2 Over-Temperature Protection and UVLO
      5. 8.3.5 Drive Strength Adjustment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Paralleling GaN Devices
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range, 9.5 V < VDD < 18 V, LPM = 5 V, VNEG = -14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GaN POWER
TRANSISTOR
RDS,ON On-state Resistance TJ = 25°C 50 mΩ
TJ = 125°C 78
VSD Third-quadrant mode source-drain voltage IN = 0 V, ISD = 0.1 A 4.9 V
IN = 0 V, ISD = 10 A 6.8
Idss Drain Leakage Current VDS =600V, TJ = 25°C 1 uA
VDS =600V, TJ = 125°C 10
Coss GaN output capacitance IN = 0 V, VDS = 400 V, FSW = 250 kHz 89 pF
Coss,er Effective output capacitance, energy related IN = 0 V, VDS =0-400 V 119 pF
Coss,tr Effective output capacitance, time related ID = 5 A, IN = 0 V, VDS = 0-400 V 181 pF
Qrr Reverse recovery charge VR = 400 V, ISD = 5 A, dISD/dt = 1 A/ns 0 nC
DRIVER SUPPLY
IVDD,LPM Quiescent current, ultra-low-power mode VLPM = 0 V, VDD = 12 V 80 95 µA
IVDD,Q Quiescent current (average) Transistor held off, RDRV=40 kΩ 0.5 mA
Transistor held on, RDRV=40 kΩ 0.5
IVDD,op Operating current VDD = 12 V, FSW = 500 KHz, RDRV=40 kΩ, 50% duty cycle 27 mA
V+5V 5V LDO output voltage VDD = 12 V 4.7 5.3 V
VNEG Negative Supply 30-mA load current -13.9 V
BUCK BOOST
CONVERTER
IDCDC,PK Peak inductor current IOUT = 20 mA, VIN = 12 V, VOUT = -14 V 250 350 mA
ΔVNEG DC-DC output ripple voltage, pk-pk CNEG = 2.2 µF, IOUT = 20 mA 50 mV
DRIVER INPUT
VIH Input pin, LPM pin, logic high threshold 2.5 V
VIL Input pin, LPM pin, low threshold 0.8 V
VHYST Input pin, LPM pin, hysteresis 0.8 V
RIN,L Input pull-down resistance 150 kΩ
RLPM LPM pin pull-down resistance 150 kΩ
UNDERVOLTAGE LOCKOUT
VDD,(ON) VDD turnon threshold Turn-on voltage 9.1 V
VDD,(OFF) VDD turnoff threshold Turn-off voltage 8.5 V
ΔVDD,UVLO UVLO Hysteresis 550 mV
FAULT
Itrip Current Fault Trip Point 40.4 60.8 77.6 A
Ttrip Temperature Trip Point Trip point 165 °C
TtripHys Temperature Trip Hysteresis 20 °C