Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in LMG3425R050. As explained in Overtemperature Shutdown Protection, ideal-diode mode provides the best GaN FET protection when the GaN FET is overheating.

OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the GaN FET. The power system may not have the capability to shut itself down, in response to the LMG3425R050 asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate drive signals but the inductive elements continue to force current flow while they discharge.

The OTSD-IDM state machine is shown in Figure 7-7. Each state is assigned a state number in the upper right side of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar states use the same state number.

Figure 7-7 Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine

1. The LMG3425R050 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank time expires, the device moves to OTSD-IDM state #2.
2. For OTSD-IDM state #2, OTSD-IDM keeps the GaN FET off if it is coming from OTSD-IDM state #1 and turns the GaN FET off if it is coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain voltage in OP-IDM state #2. It is looking for a negative drain voltage which means third-quadrant current is flowing. This is also the starting state when the device enters OTSD. After a negative GaN FET drain voltage is detected, the device moves to OTSD-IDM state #3
3. OTSD-IDM turns on the GaN FET in OTSD-IDM state #3. OTSD-IDM monitors the drain current in this state. If first-quadrant drain current is detected, the device moves to OTSD-IDM state #2.

State #1 is used to protect against shoot-through current in a similar manner to OP-IDM state #1. The difference is that state #1 in the OTSD-IDM state machine waits for a fixed time period before proceeding to state #2. The fixed time period is to give the opposite-side switch time to switch and create a positive drain voltage. A fixed time is used to avoid a stuck condition for cases where a positive drain voltage is not created.

State #1 will help protect against shoot-through currents if the converter continues switching when the LMG3425R050 enters OTSD. Meanwhile, if the converter initiates switching with the LMG3425R050 already in OTSD, shoot-through current protection can be obtained by switching the OTSD device first to force it to progress though state #1. For example, the synchronous rectifier in a boost PFC can go into OTSD during initial input power application as the inrush current charges the PFC output cap. A shoot-through current event can be avoided if converter switching begins by switching the synchronous rectifier FET before switching the boost PFC FET.

If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode mode state machine. This allows all the inductive elements to discharge, when the power system shuts off, with minimum discharge stress created in the GaN FET.

Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current events. There are degenerate cases, such as the LMG3425R050 losing its IN signal during converter operation, which can expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario. If OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET would instead be exposed to excessive off-state third-quadrant losses.