JAJSOK0 November   2022 LMG3522R030

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-On Times
      2. 7.1.2 Turn-Off Times
      3. 7.1.3 Drain-Source Turn-On Slew Rate
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN FET Operation Definitions
      2. 8.3.2  Direct-Drive GaN Architecture
      3. 8.3.3  Drain-Source Voltage Capability
      4. 8.3.4  Internal Buck-Boost DC-DC Converter
      5. 8.3.5  VDD Bias Supply
      6. 8.3.6  Auxiliary LDO
      7. 8.3.7  Fault Detection
        1. 8.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 8.3.7.2 Overtemperature Shutdown
        3. 8.3.7.3 UVLO Protection
        4. 8.3.7.4 Fault Reporting
      8. 8.3.8  Drive Strength Adjustment
      9. 8.3.9  Temperature-Sensing Output
      10. 8.3.10 Ideal-Diode Mode Operation
        1. 8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
    4. 8.4 Start Up Sequence
    5. 8.5 Safe Operation Area (SOA)
      1. 8.5.1 Safe Operation Area (SOA) - Repetitive SOA
    6. 8.6 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Using an Isolated Power Supply
      2. 9.4.2 Using a Bootstrap Diode
        1. 9.4.2.1 Diode Selection
        2. 9.4.2.2 Managing the Bootstrap Voltage
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Solder-Joint Reliability
        2. 9.5.1.2 Power-Loop Inductance
        3. 9.5.1.3 Signal-Ground Connection
        4. 9.5.1.4 Bypass Capacitors
        5. 9.5.1.5 Switch-Node Capacitance
        6. 9.5.1.6 Signal Integrity
        7. 9.5.1.7 High-Voltage Spacing
        8. 9.5.1.8 Thermal Recommendations
      2. 9.5.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Export Control Notice
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1.2 Turn-Off Times

The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off fall time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the LHB load current.