JAJSS46 November   2023 LMG3612

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Input Control Pin (IN)
      4. 7.3.4 AUX Supply Pin
        1. 7.3.4.1 AUX Power-On Reset
        2. 7.3.4.2 AUX Under-Voltage Lockout (UVLO)
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10 V ≤ VAUX ≤ 26 V; VIN = 0 V; RRDRV = 0 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
RDS(on) Drain-source (D to S) on resistance VIN = 5 V, ID = 4.2 A, TJ = 25°C 120 mΩ
VIN = 5 V, ID = 4.2 A, TJ = 125°C 214
IDSS Drain (D to S) leakage current VDS = 650 V, TJ = 25°C 3 µA
VDS = 650 V, TJ = 125°C 15
QOSS Output (D to S) charge VDS = 400 V 28.3 nC
COSS Output (D to S) capacitance 43.9 pF
EOSS Output (D to S) capacitance stored energy 3.74 µJ
COSS,er Energy related effective output (D to S) capacitance 46.7 pF
COSS,tr Time related effective output (D to S) capacitance VDS = 0 V to 400 V 70.2 pF
QRR Reverse recovery charge 0 nC
IN
VIT+ Positive-going input threshold voltage 1.7 2.45 V
VIT– Negative-going input threshold voltage 0.7 1.3 V
Input threshold voltage hysteresis 1 V
Pull-down input resistance 0 V ≤ VPIN ≤ 3 V 200 400 600 kΩ
Pull-down input current 10 V ≤ VPIN ≤ 26 V; VAUX = 26 V 10 µA
OVERTEMPERATURE PROTECTION
Temperature fault – postive-going threshold temperature 165 °C
Temperature fault – negative-going threshold temperature 145 °C
Temperature fault – threshold temperature hysteresis 20 °C
FLT
Low-level output voltage FLT sinking 1 mA while asserted 200 mV
Off-state sink current VFLT = VAUX while de-asserted 1 µA
AUX
VAUX,T+(UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V
UVLO – negative-going threshold voltage 8.6 9.0 9.4 V
UVLO – threshold voltage hysteresis 250 mV
Quiescent current 55 120 µA
Operating current VIN = 0 V or 5 V, VDS = 0 V, fIN = 500 kHz 2.2 mA