8.3.1 Loss of Signal Detector

The LMH0318 supports two high speed differential input ports, with internal 100 Ω terminations. The inputs must be AC coupled. The external AC coupling capacitor value should take into account the pathological low frequency content. For most applications, the RC time constant of 4.7 µF AC coupling capacitor plus the 50 Ω termination resistor is capable of handing the pathological video pattern's low frequency content.

The signal detect circuit is designed to assert when data traffic with a certain minimum amplitude is present at the input of the device. It is also designed to de-assert, or remain de-asserted, when there is noise below certain amplitude at the input to the device.

The LMH0318 has two signal detect circuits, one for each input. Each signal detect threshold can be set independently. By default, both signal detects are powered on. The user selects IN1 or IN0 through SMBus/SPI interface.

8.3.2 Continuous Time Linear Equalizer (CTLE)

The LMH0318 has receive-side equalization, and a key part is the Continuous Time Linear Equalizer (CTLE). This circuit operates on the received differential signal and compensates for frequency-dependent loss due to the transmission media. The CTLE applies gain to the input signal. This gain varies over frequency: higher frequencies are boosted more than lower frequencies. The CTLE works to restore the input signal to full amplitude across a wide range of frequencies.

The CTLE consists of 4 stages with each stage having two boost control bits. This allows 256 different boost settings. CTLE boost levels are determined by summing the boost levels of the 4 stages. The CTLE is configured manually. See LMH0318 Programming Guide (SNLU183) on how to quickly select the most appropriate CTLE boost setting.

There are two CTLEs, one for each input, IN0 and IN1. Only one CTLE is enabled at a time, according to the user input channel selection. If IN0 is selected, the CTLE for IN0 is powered on and the IN1 CTLE is powered off. The CTLE is able to handle low loss channels without over-equalizing by bypassing the CTLE.

8.3.3 2:1 Multiplexer

A 2:1 input multiplexor connects IN0 and IN1 to the CDR. By default, IN0 is selected. To select IN1, the 2:1 multiplexer must be set. See LMH0318 Programming Guide (SNLU183) for detailed settings.

8.3.4 Clock and Data Recovery

By default, the equalized data is fed into the CDR for clock and data recovery. The CDR consists of a reference-less Phase Frequency Detector (PFD), Charge Pump (CP), Voltage Controlled Oscillator (VCO), and Output Data Multiplexer (Mux).

The inputs to the Phase and Frequency Detector (PFD) are the data after the CTLE as well as I and Q clocks from the VCO. The LMH0318 will attempt to lock to the incoming data by tuning the VCO to phase-lock to the incoming data rate.

The supported data rates are listed in the following table. See LMH0318 Programming Guide (SNLU183) for further information on configuring the LMH0318 for different data rates.

8.3.5 Eye Opening Monitor (EOM)

The LMH0318 has an on-chip eye opening monitor (EOM) which can be used to analyze, monitor, and diagnose the performance of the link. The EOM operates on the post-equalized waveform, just prior to the data sampler. Therefore, it captures the effects of all the equalization circuits within the receiver before the data is reclocked. The EOM is operational for 1.485 Gbps and higher data rates.

The EOM monitors the post-equalized waveform in a time window that spans one unit interval and a configurable voltage range that spans up to ±400 mV differential. The time window and voltage range are divided into 64 steps, so the result of the eye capture is a 64 × 64 matrix of “hits,” where each point represents a specific voltage and phase offset relative to the main data sampler. The number of “hits” registered at each point needs to be taken in context with the total number of bits observed at that voltage and phase offset in order to determine the corresponding probability for that point. The number of bits observed at each point is configurable.

A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye opening (HEO) represents the width of the post-equalized eye at 0 V differential amplitude, measured in unit intervals or picoseconds. The vertical eye opening (VEO) represents the height of the post-equalized eye, measured midway between the mean zero crossing of the eye. This position in time approximates the CDR sampling phase.

The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of ways. Two common ways to visualize this data are shown in Figure 20 and Figure 21. These diagrams depict examples of an eye monitor plot implemented by software. The first plot is an example of using the EOM data to plot a basic eye using ASCII characters, which can be useful for simple diagnostics software. The second plot shows the first derivative of the EOM data, revealing the density of hits and the actual waveforms and crossing that comprise the eye.

8.3.6 Fast EOM

Fast EOM is a mechanism that provides an option to read out EOM through SPI/SMBus interfaces by reading the hits observed for each point of 64 × 64 points matrix. Since SPI interface operates at faster clock rate than SMBus interface, the SPI master will have to wait until the EOM start bit, reg 0x24[0], goes low. This indicates EOM samples are available and the SPI master can proceed to read register 0x25 and 0x26. See SPI Fast EOM Operation and LMH0318 Programming Guide (SNLU183) for further details of Fast EOM operation.

8.3.7 LMH0318 Device Configuration

The control pins can be used to configure different operations depending on the functional modes as described in Table 2.

1. 1 kΩ to VDD: This puts the part in SPI mode
2. Float (Default): Reserved
3. 20 kΩ to GND: Reserved
4. 1 kΩ to GND: This puts the part in SMBus mode

8.3.7.6 SMBus READ/WRITE Transaction

The System Management Bus (SMBus) is a two-wire serial interface through which various system component chips can communicate with the master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the Master to all of the Slave devices on the bus. SDA is a bidirectional data signal between the Master and Slave devices. The LMH0318 SMBUS SCL and SDA signals are open drain and require external pull up resistors.

Start and Stop:

The Master generates Start and Stop conditions at the beginning and end of each transaction.

• Start: High to low transition (falling edge) of SDA while SCL is high
• Stop: Low to high transition (rising edge) of SDA while SCL is high

Figure 3. Start and Stop Conditions

The Master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the device pulls SDA low, while a NACK is recorded if the line remains high.

Figure 4. Acknowledge (ACK)

Writing data from a master to a slave comprises of 3 parts as noted in figure Figure 5

• The master begins with start condition followed by the slave device address with the R/W bit cleared
• The 8-bit register address that will be written
• The data byte to write

Figure 5. SMBus Write Operation

SMBus read operation consists of four parts

• The master initiates the read cycle with start condition followed by slave device address with the R/W bit cleared
• The 8-bit register address that is to be read
• After acknowledgment from the slave, the master initiates a re-start condition
• The slave device address is resent followed with R/W bit set
• After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is high if there are no more bytes to read

Figure 6. SMBus Read Operation

Figure 7. SMBus Timing Parameters

8.3.7.7 SPI Mode

The SPI (Serial Peripheral Interface) bus standard can be used to control the device. The SPI Mode is enabled when MODE_SEL Pin 1 is pulled high through the 1-kΩ resistor. The SPI bus comprises of 4 pins: Pin 2, Pin 3, Pin 4, and Pin 15:

1. MOSI Pin 4: Master Output Slave Input. Configured as toggling input.
2. MISO Pin 15: Master Input, Slave Output: Configured as a toggling output
3. SS_N Pin 2: Slave Select (active low). Configured as toggling input.
4. SCK Pin 3: Serial clock (output from master). Configured as toggling input.

The maximum operating speed supported on the SPI bus is 20 MHz.

8.3.7.7.1 SPI READ/WRITE Transaction

Each SPI transaction to a single device is 17 bits long and is framed by SS_N asserted low. The MOSI input is ignored and the MISO output is floated whenever SS_N is de-asserted (High).

The bits are shifted in left-to-right. The first bit is R/W, so it is 1 for reads and 0 for writes. Bits A7-A0 are the 8-bit register address, and bits D7-D0 are the 8-bit read or write data. The prior SPI command, address, and data are shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously when SS_N becomes asserted.

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 8. MOSI Format

8.3.7.7.2 SPI Write Transaction Format

For SPI writes, the R/W bit is 0. SPI write transactions are 17 bits per device, and the command is executed on the rising edge of SS_N, as shown in Figure 9. The SPI transaction always starts on the rising edge of the clock.

Figure 9. MOSI Write Sequence

0

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

The signal timing for a SPI Write transaction is shown in Figure 10. The “prime” values on MISO (for example, A7‟) reflect the contents of the shift register from the previous SPI transaction, and are a "don’t-care" for the current transaction.

Figure 10. Signal Timing for a SPI Write Transaction

8.3.7.7.3 SPI Read Transaction Format

An SPI read transaction is 34 bits per device consisting of two 17-bit frames. The first 17-bit read transaction, first frame, shifts in the address to be read, followed by a dummy transaction, second frame, to shift out the 17-bit read data. The R/W bit is 1 for the read transaction, as shown in Figure 11.

The first 17 bits from the read transaction specifies 1-bit of RW and 8-bits of address A7-A0. The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on address 0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in the last 8 bits of the MISO output.

The signal timing for a SPI read transaction is shown in Figure 11. As with the SPI write, the “prime” values on MISO during the first 16 clocks are a don’t-care for this portion of the transaction. Note, that the values shifted out on MISO during the last 17 clocks reflect the read address and 8-bit read data for the current transaction.

Figure 11. Signal Timing for a SPI Read Transaction

8.3.7.8 SPI Daisy Chain

The LMH0318 includes an enhanced SPI controller that supports daisy-chaining the serial configuration data among multiple LMH0318 devices. The LMH0318 device supports SPI Daisy Chain between devices with an 8-bit SPI addressing scheme. Each LMH0318 device is directly connected to the SCK and SS_N pins of the Host. However, only the first LMH0318 device in the chain is connected to the Host’s MOSI pin, and only the last device in the chain is connected to the Host’s MISO pin. The MOSI pin of each intermediate LMH0318 device in the chain is connected to the MISO pin of the previous LMH0318 device, thereby creating a serial shift register. This architecture is shown in Figure 12.

Figure 12. Daisy-Chain Configuration

In a daisy-chain configuration of N LMH0318 devices, the Host conceptually sees a long shift register of length 17xN. Therefore the length of a Basic SPI Transaction, as described above, is 17xN; in other words, SS_N is asserted for 17xN clock cycles.

8.3.7.8.1 SPI Daisy Chain Write Example

The following example make some assumptions:

The daisy-chain is 3 LMH0318 devices long, comprising Devices 1, 2, and 3 as shown in Figure 12. Therefore, each Basic SPI Transaction is 17x3 = 51 clocks long.

In Figure 13, the following occurs at the end of the transaction:

• Write 0x5A to register 0x12 in Device 3
• Write 0x3C to register 0x34 in Device 2
• Write 0x00 to register 0x56 in Device 1

Note that the bits are shifted out of MOSI left to right. The MISO pin is not shown as it reflects shift register contents from a prior transaction.

Figure 13. MOSI Write Example

8.3.7.8.2 SPI Daisy Chain Write Read Example

In Figure 14 and Figure 15, the following occurs at the end of the first transaction:

• Write 0x22 to register 0x01 in Device 3
• Latch the data from register 0x34 in Device 2
• Write 0x44 to register 0x76 in Device 1

Figure 14. SPI Daisy Chain Write Read First Frame Illustration

Figure 15. SPI Daisy Chain Write Read second Frame Illustration

8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration

A useful operation for the Host may be to detect the length of the daisy-chain. This is a simple matter of shifting in a series of known data values (0x7F, 0xAA) in the example in Figure 16. After N+1 writes, the known data value will begin to appear on the Host's MISO pin.

Figure 16. MOSI (Host)

8.3.8 Power-On Reset

The LMH0318 has an internal power-on reset (PoR) circuitry which initiates a self-clearing reset after the power is applied to the VDD pins.

8.5.1 Register Maps

The LMH0318 register set definition is organized into four groups:

1. Global Registers: Chip ID, Interrupt status, LOS registers
2. Receiver Registers: Equalizer boost settings and signal detect setting
3. CDR Registers: PLL control
4. Transmitter Registers: OUT0 and OUT1 parameter setting

The typical device initialization sequence for the LMH0318 includes the followings. For detailed register settings See LMH0318 Programming Guide (SNLU183).

1. Shared Register Configuration
   1. Reading device ID
   2. Selecting interrupt on to LOS pin
   3. Settings up the register to access the channel registers
2. Channel Register Configuration
   1. CDR Reset
   2. Interrupt register configuration
   3. Optional Input/Output selection
   4. Optional VOD selection
   5. CDR Reset and Release

8.5.2 Global Registers

8.5.3 Receiver Registers

8.5.4 CDR Registers

8.5.5 Transmitter Registers