JAJSFL4B April   2016  – June 2018 LMH0324

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Pins
      2. 7.3.2 Carrier Detect
      3. 7.3.3 Adaptive Cable Equalizer
      4. 7.3.4 Launch Amplitude
      5. 7.3.5 Input-Output Mux Selection
      6. 7.3.6 Output Function Control
      7. 7.3.7 Output Driver Amplitude and De-Emphasis Control
      8. 7.3.8 Additional Programmability
        1. 7.3.8.1 Cable Length Indicator (CLI)
        2. 7.3.8.2 Digital MUTEREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH0324 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CableEQ/Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Recommended VOD and DE Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RTW|24
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD1P8V Power Consumption(3) Measured with PRBS-10, VOD = Default, only OUT0 enabled, 2.97 Gbps, VIN=VDD_LDO=VDDIO=1.8 V 78 mW
Measured with PRBS-10, VOD = Default, OUT0 and OUT1 enabled, 2.97 Gbps, VIN=VDD_LDO=VDDIO=1.8 V 100 mW
PDZ1P8V Power Consumption(3) Power Save Mode: No input signal, VIN=VDD_LDO=VDDIO=1.8 V 15 mW
PD2P5V Power Consumption(3) Measured with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled, VIN=VDDIO=2.5 V 128 mW
Measured with PRBS-10, 2.97 Gbps, VOD = Default, OUT0 and OUT1 enabled, VIN=VDDIO=2.5 V 147 mW
PDZ2P5V Power Consumption(3) Power Save Mode: No input signal, VIN=VDDIO=2.5 V 28 mW
IDD Current Consumption(3) Measured at 1.8 V supply with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled 43 55 mA
Measured at 2.5 V supply with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled 51 71
IDDZ_1P8V Current Consumption(3) Forced Power Save Mode: MODE_SEL = LEVEL-H, Measured at 1.8 V supply, VIN=VDD_LDO=VDDIO=1.8 V 4 10 mA
VLDO LDO 1.8 V Output Voltage VIN = VDDIO = 2.5 V 1.71 1.8 1.89 V
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V or 1.8 V 0.7 x VDDIO VDDIO + 0.3 V
2-Level Input (SCL, SDA), VDDIO = 2.5 V 0.7 x VDDIO 3.6
VIL Low Level Input Voltage 2-Level Input (SS_N, SCK, MOSI) VDDIO = 2.5 V or 1.8 V -0.3 0.3 x VDDIO V
2-Level Input (SCL, SDA), VDDIO = 2.5 V 0 0.3 x VDDIO
VOH High Level Output Voltage IOH = -2 mA, (MISO), VDDIO = 2.5 V or 1.8 V 0.8 x VDDIO VDDIO V
VOL Low Level Output Voltage IOL = 2 mA, (MISO), VDDIO = 2.5 V or 1.8 V 0 0.2 x VDDIO V
IOL = 3 mA, (CD_N, SCL, SDA), VDDIO = 2.5 V 0 0.4
IIH Input High Leakage Current SPI Mode: LVCMOS (SS_N, SCK, MOSI), Vinput = VDDIO 15 µA
SMBus Mode: LVCMOS (CD_N, SCL, SDA), Vinput = VDDIO 10
IIL Input Low Leakage Current SPI Mode: LVCMOS (SS_N), Vinput = VSS -40 µA
SPI Mode: LVCMOS (SCK, MOSI), Vinput = VSS -15
SMBus Mode: LVCMOS (CD_N, SCL, SDA), Vinput = VSS -10
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V4_LVL_H LEVEL-H Input Voltage External pull-up 1 kΩ to VDDIO VDDIO V
V4_LVL_F LEVEL-F Default Voltage Float, VDDIO = 2.5 V or 1.8 V 2/3 x VDDIO V
V4_LVL_R LEVEL-R Input Voltage External pull-down 20 kΩ to VSS, VDDIO = 2.5 V or 1.8 V 1/3 x VDDIO V
V4_LVL_L LEVEL-L Input Voltage External pull-down 1 kΩ to VSS 0 V
I4_LVL_IH Input High Leakage Current 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VDDIO 20 45 80 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VDDIO 20 45 80
I4_LVL_IL Input Low Leakage Current 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VSS -160 –93 -40 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VSS -160 –93 -40
RECEIVER SPECIFICATIONS (IN0+)
RIN0_TERM DC Input Termination IN0+ and IN0- to VSS 63 75 87 Ω
RLIN0 Input Return Loss Reference to 75 Ω(1) S11, 5 MHz to 1.485 GHz –20 dB
S11, 1.485 GHz to 3 GHz –18
VIN0_CM IN0 DC Common Mode Voltage Input common mode voltage at IN0+ to VSS 1.4 V
VWANDER Input DC Wander SD signal at IN0+, Input launch amplitude = 0.8 Vp-p 100 mVp-p
HD, 3G signal at IN0+, Input launch amplitude = 0.8 Vp-p 50 mVp-p
OUTPUT DRIVERS (OUT0± OR OUT1±)
VOD Output Differential Voltage(4) 8T pattern, see Figure 6, VOD_DE = LEVEL-H
SD, HD, and 3G		 410 mVp-p
8T pattern, see Figure 6,VOD_DE = LEVEL-F
SD, HD, and 3G		 485 560 620
8T pattern, see Figure 6, VOD_DE = LEVEL-R
SD, HD, and 3G		 635
8T pattern, see Figure 6, VOD_DE = LEVEL-L
SD, HD, and 3G		 810
VODDE De-emphasized Output Differential Voltage(4) 8T pattern, see Figure 7, VOD_DE = LEVEL-H
SD, HD, and 3G		 410
8T pattern, see Figure 7, VOD_DE = LEVEL-F Default
SD, HD, and 3G 		500
8T pattern, see Figure 7, VOD_DE = LEVEL-R
SD, HD, and 3G 		480
8T pattern, see Figure 7, VOD_DE = LEVEL-L
SD, HD, and 3G 		480
ROUT_TERM DC Output Differential Termination Measured across OUTn+ and OUTn- 80 100 120 Ω
tR/tF Output Rise or Fall Time (2) 20% - 80% using 8T Pattern 270 Mbps, 1.485 Gbps, 2.97 Gbps, measured after 1 inch trace 45 ps
DR Input Data Rate 125 Mbps
Gbps
2.97
JITRATE Jitter for Various Cable Length(2) 2.97 Gbps B1694A: 0 – 150 m 0.25 UI
2.97 Gbps B1694A: 150 m 0.25 0.4
2.97 Gbps B1694A: 150 - 200 m 0.55
1.485 Gbps B1694A: 0 – 200 m 0.2
1.485 Gbps B1694A: 200 m 0.2 0.35
1.485 Gbps B1694A: 200 – 300 m 0.55
270 Mbps B1694A: 0 – 400 m 0.2
270 Mbps B1694A: 400 m 0.15 0.3
270 Mbps B1694A: 400 – 600 m 0.35
TADAPT Equalizer Adapt Time - Signal detect to Adaptation Completed PRBS-10, Belden 1694A coax cable, nominal launch amplitude of 0.8 Vpp, 2.97 Gbps 5 ms
(1) This parameter was measured with an LMH0324-18EVM.
(2) This parameter was measured with an LMH0324-18EVM.
(3) Measured with RSV_L tied to VSS.
(4) ATE production tested with DC method.