JAJSI47B April   2017  – October 2019 LMH0397

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Equalizer Mode (EQ Mode)
      2. 8.1.2 Cable Driver Mode (CD Mode)
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Pins and Thresholds
      2. 8.3.2  Equalizer (EQ) and Cable Driver (CD) Mode Control
        1. 8.3.2.1 EQ/CD_SEL Control
        2. 8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control
      3. 8.3.3  Input Carrier Detect
      4. 8.3.4  –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
      5. 8.3.5  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ Mode)
        2. 8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
      6. 8.3.6  Clock and Data (CDR) Recovery
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Control
        1. 8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD Mode, SDI_OUT+ in EQ or CD Mode)
          1. 8.3.9.1.1 Output Amplitude (VOD)
          2. 8.3.9.1.2 Output Pre-Emphasis
          3. 8.3.9.1.3 Output Slew Rate
          4. 8.3.9.1.4 Output Polarity Inversion
        2. 8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD Mode)
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable EQ Index (CEI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transaction
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
        2. 8.4.2.2 SPI Write Transaction Format
        3. 8.4.2.3 SPI Read Transaction Format
        4. 8.4.2.4 SPI Daisy Chain
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SMPTE Requirements and Specifications
      2. 9.1.2 Low-Power Optimization in CD Mode
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional I/O
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Cable Equalizer With Loop-Through
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stack-Up and Ground References
      2. 11.1.2 High-Speed PCB Trace Routing and Coupling
        1. 11.1.2.1 SDI_IO± and SDI_OUT±
        2. 11.1.2.2 IN0± and OUT0±
      3. 11.1.3 Anti-Pads
      4. 11.1.4 BNC Connector Layout and Routing
      5. 11.1.5 Power Supply and Ground Connections
      6. 11.1.6 Footprint Recommendations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 輸出管理に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PDEQ_MODE Power dissipation, EQ Mode,
Measured with PRBS10,
CDR Locked to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor disabled 		SDI_OUT± disabled
OUT0± enabled		 275 mW
SDI_OUT± enabled
OUT0± enabled		 405 mW
PDCD_MODE Power dissipation, CD Mode,
Measured with PRBS10,
CDR Locked to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor disabled		 SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled		 290 mW
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled		 335 mW
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled		 415 mW
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled		 460 mW
PDZ Power dissipation,
Power Save Mode		 EQ Mode, Power Save Mode,
ENABLE = H, no signal applied at SDI_IO+		 25 mW
CD Mode, Power Save Mode,
ENABLE = H, no signal applied at IN0±		 25
IDDEQ_MODE Current consumption, EQ Mode,
Measured with PRBS10,
CDR Locked to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor disabled 		SDI_OUT± disabled
OUT0± enabled		 110 131 mA
SDI_OUT± enabled
OUT0± enabled		 162 191 mA
IDDCD_MODE Current consumption, CD Mode,
Measured with PRBS10,
CDR Locked to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor disabled
CD Mode		 SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled		 116 137 mA
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled		 134 157 mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled		 166 196 mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled		 184 217 mA
IDDZ Current consumption,
Power Save Mode		 EQ Mode, Power Save Mode,
ENABLE = H, no signal applied at SDI_IO+		 10 mA
CD Mode, Power Save Mode,
ENABLE = H, no signal applied at IN0±		 10
IDDZ_PD Current consumption,
Power-Down Mode		 EQ Mode, Power-Down Mode,
ENABLE = L, no signal applied at SDI_IO+		 10 30 mA
CD Mode, Power-Down Mode,
ENABLE = L, no signal applied at IN0±		 10 30
IDDTRANS_EQ Current consumption, EQ Mode
CDR acquiring lock to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor enabled 		SDI_OUT± disabled
OUT0± enabled		 189 mA
SDI_OUT± enabled
OUT0± enabled		 257 mA
IDDTRANS_CD Current consumption, CD Mode
CDR acquiring lock to 2.97 Gbps,
VOD = default,
HEO/VEO lock monitor enabled		 SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled		 200 mA
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled		 222 mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled		 271 mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled		 290 mA
LVCMOS DC SPECIFICATIONS
VIH Logic high input voltage 2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE) 0.72 × VIN VIN + 0.3 V
2-level input (SCL, SDA) 0.7 × VIN 3.6
VIL Logic low input voltage 2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE, SCL, SDA) 0 0.3 × VIN V
VOH Logic high output voltage IOH = –2 mA, (MISO) 0.8 × VIN VIN V
VOL Logic low output voltage IOL = 2 mA, (MISO) 0 0.2 × VIN V
IOL = 3 mA, (LOCK_N, SDA) 0.4
IIH Input high leakage current
(Vinput = VIN)		 LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE) 15 µA
LVCMOS (OUT0_SEL) 65
LVCMOS (LOCK_N) 10
SPI mode: LVCMOS (SS_N, SCK, MOSI) 15
SMBus mode: LVCMOS (SCL, SDA) 10
IIL Input low leakage current
(Vinput = GND)		 LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE) –50 µA
LVCMOS (OUT0_SEL) –15
LVCMOS (LOCK_N) –10
SPI mode: LVCMOS (SCK, MOSI) –15
SPI mode: LVCMOS (SS_N) –50
SMBus mode: LVCMOS (SCL, SDA) –10
4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
VLVL_H LEVEL-H input voltage Measured voltage at 4-level pin with external 1 kΩ to VIN VIN V
VLVL_F LEVEL-F default voltage Measured voltage 4-level pin at default 2/3 × VIN V
V LVL_R LEVEL-R input voltage Measured voltage at 4-level pin with external 20 kΩ to VSS 1/3 × VIN V
VLVL_L LEVEL-L input voltage Measured voltage at 4-level pin with external 1 kΩ to VSS 0 V
IIH Input high leakage current
(Vinput = VIN)		 4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD) 20 45 80 µA
SMBus mode: 4-levels (ADDR0, ADDR1) 20 45 80
IIL Input low leakage current
(Vinput = GND)		 4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD) –160 –93 –40 µA
SMBus mode: 4-levels (ADDR0, ADDR1) –160 –93 –40
RECEIVER SPECIFICATIONS (SDI_IO+, EQ MODE)
RSDI_IO_TERM DC input single-ended termination SDI_IO+ and SDI_IO– to internal common mode bias 63 75 87 Ω
RLSDI_IO_S11 Input return loss at SDI_IO+ reference to 75 Ω(1) S11, 5 MHz to 1.485 GHz –30 dB
S11, 1.485 GHz to 3 GHz –22
VSDI_IO_CM SDI_IO+ DC common-mode voltage Input DC common-mode voltage at SDI_IO+ or SDI_IO– to GND 1.4 V
VSDI_IO_WANDER Input DC wander SD, input signal at SDI_IO+,
Input launch amplitude = 800 mVp-p		 100 mVp-p
HD, 3G input signal at SDI_IO+,
Input launch amplitude = 800 mVp-p		 50
RECEIVER SPECIFICATIONS (IN0±, CD MODE)
RIN0_TERM DC input differential termination Measured across IN0+ to IN0– 80 100 120 Ω
RLIN0_SDD11 Input differential return loss(1) SDD11, 10 MHz to 2.8 GHz –22 dB
RLIN0_SCD11 Differential to common-mode input conversion(1) SCD11, 10 MHz to 11.1 GHz –21 dB
VIN0_CM DC common-mode voltage Input common-mode voltage at IN0+ or IN0– to GND 2.06 V
CDON_IN0 Signal detect (default)
Assert ON threshold level for IN0±		 2.97 Gbps, EQ and PLL pathological pattern 20 mVp-p
CDOFF_IN0 Signal detect (default)
Deassert OFF threshold level for IN0±		 2.97 Gbps, EQ and PLL pathological pattern 18 mVp-p
DRIVER OUTPUT (SDI_IO+ AND SDI_OUT+, CD MODE)
ROUT_TERM DC output single-ended termination SDI_IO+ and SDI_IO–,
SDI_OUT+ and SDI_OUT– to VIN		 63 75 87 Ω
VODCD_OUTP Output single-ended voltage Measure AC signal at SDI_IO+ and SDI_OUT+, with SDI_IO– and SDI_OUT– AC terminated with 75 Ω
SDI_VOD = H		 840 mVp-p
SDI_VOD = F 720 800 880
SDI_VOD = R 880
SDI_VOD = L 760
VODCD_OUTN Output single-ended voltage Measure AC signal at SDI_IO– and SDI_OUT-, with SDI_IO+ and SDI_OUT+ AC terminated with 75 Ω
SDI_VOD = H		 840 mVp-p
SDI_VOD = F 720 800 880
SDI_VOD = R 880
SDI_VOD = L 760
PRECD_OUTP Output pre-emphasis Output pre-emphasis boost amplitude at SDI_IO+ and SDI_OUT+, programmed to maximum setting through register, measured at SDI_VOD=F 2 dB
PRECD_OUTN Output pre-emphasis Output pre-emphasis boost amplitude at SDI_IO– and SDI_OUT–, programmed to maximum setting through register, measured at SDI_VOD=F 2 dB
tR_F_SDI Output rise and fall time(1) Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
2.97 Gbps		 59 67 ps
1.485 Gbps 60 73
270 Mbps 400 550 700
tR_F_DELTA Output rise and fall time mismatch(1) Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
2.97 Gbps		 0.8 11 ps
1.485 Gbps 0.8 12
270 Mbps 72 150
VOVERSHOOT Output overshoot or undershoot Measured with PRBS10 pattern, default VOD, default pre-emphasis enabled(2)
3G/HD/SD		 5%
VDC_OFFSET DC offset 3G/HD/SD ±0.2 V
VDC_WANDER DC wander 3G/HD/SD with EQ pathological pattern 20 mV
RLCD_S22 Output return loss at SDI_IO+ and SDI_OUT+ reference to 75 Ω(1) S22, 5 MHz to 1.485 GHz –25 dB
S22, 1.485 GHz to 3 GHz –22 dB
DRIVER OUTPUT (OUT0±, EQ AND CD MODE)
ROUT0_TERM DC output differential termination Measured across OUT0+ and OUT0– 80 100 120 Ω
VODOUT0 Output differential voltage at OUT0± Measured with 8T pattern
HOST_EQ0 = H		 410 mVp-p
HOST_EQ0 = F 485 560 620
HOST_EQ0 = R 635
HOST_EQ0 = L 810
VODOUT0_DE De-emphasized output differential voltage at OUT0± Measured with 8T pattern
HOST_EQ0 = H		 410 mVp-p
HOST_EQ0 = F 550
HOST_EQ0 = R 545
HOST_EQ0 = L 532
tR/tF Output rise and fall time Measured with 8T Pattern, 20% to 80% amplitude 45 ps
RLOUT0-SDD22 Output differential return loss(1) Measured with the device powered up and outputs a 10-MHz clock signal.
SDD22, 10 MHz to 2.8 GHz		 –24 dB
RLOUT0-SCC22 Output common-mode return loss(1) Measured with the device powered up and outputs a 10-MHz clock signal.
SCC22, 10 MHz to 4.75 GHz		 –12 dB
VOUT0_CM AC common-mode voltage on OUT0±(1) Default setting, PRBS31, 2.97 Gbps 8 mV (rms)
RECLOCKER OUTPUT JITTER (EQ MODE)
TJEQ_MODE Total jitter, reclocked output(1) Measured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10,
TX launch amplitude = 800 mVp-p before cable to SDI_IO+
2.97 Gbps: 200-m Belden 1694A 		0.1 UIp-p
1.485 Gbps: 300-m Belden 1694A 0.1
270 Mbps: 600-m Belden 1694A 0.11
TJRAW Total jitter, with CDR bypassed Measured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10,
TX launch amplitude = 800 mVp-p before cable to SDI_IO+
125 Mbps: 600-m Belden 1694A		 0.2 UIp-p
RECLOCKER OUTPUT JITTER (CD MODE)
AJCD_MODE Alignment jitter(1) Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled
PRBS10, 3G/HD/SD		 0.1 0.14 UI
TMJCD_MODE Timing jitter(1) Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled
PRBS10, 3G/HD/SD		 0.45 UI
RECLOCKER SPECIFICATIONS (EQ MODE UNLESS OTHERWISE SPECIFIED)
LOCKRATE Reclocker lock data rates SMPTE 3G, /1 2.97 Gbps
SMPTE 3G, /1.001 2.967
SMPTE HD, /1 1.485
SMPTE HD, /1.001 1.4835
SMPTE SD, /1 270 Mbps
BYPASSRATE Reclocker automatically goes to bypass MADI 125 Mbps
BWPLL PLL Bandwidth Applied 0.2 UI input sinusoidal jitter, measure –3-dB bandwidth on input-to-output jitter transfer
2.97 Gbps		 5 MHz
1.485 Gbps 3
270 Mbps 1
JPEAKING PLL jitter peaking 2.97 Gbps, 1.485 Gbps, 270 Mbps <0.3 dB
JTOL_IN SDI_IO+ input jitter tolerance Sinusoidal jitter tolerance,
tested at 3G,
SJ amplitude swept from 1 MHz to 80 MHz, tested at BER ≤ 1E-12, cable equalizer at SDI_IO+ bypassed		 0.65 UI
TLOCK Lock time SMPTE supported data rates, disable HEO/VEO monitor, cable equalizer at SDI_IO+ bypassed 5 ms
TADAPT EQ adapt time at EQ Mode Adaptation time for cable equalizer at SDI_IO+, reclocker bypassed 5 ms
TEMPLOCK VCO temperature lock range Measured with temperature ramp of 5°C per minute, ramp up and down, –40°C to 85°C operating range at 2.97 Gbps 125 °C
TLATEQ_MODE Reclocker latency at EQ Mode Measured from SDI_IO+ to OUT0, 2.97 Gbps, SDI_IO+,
75-m Belden 1694A at SDI_IO+		 1.4 UI + 465 ps
Measured from SDI_IO+ to SDI_OUT+, 2.97 Gbps, SDI_IO+, 75-m Belden 1694A at SDI_IO+ 1.7 UI + 415
TLATCD_MODE Reclocker latency at CD Mode Measured from IN0± to SDI_IO+, 2.97 Gbps 1.5 UI + 175 ps
Measured from IN0± to SDI_OUT+, 2.97 Gbps 1.6 UI + 130
(1) This parameter is measured with the LMH1297EVM (Evaluation board for LMH0397).
(2) VOVERSHOOT overshoot or undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The maximum value specified in Electrical Characteristics for VOVERSHOOT is based on bench evaluation across temperature and supply voltages with the LMH1297EVM.