8.3.7.6 SMBus READ/WRITE Transaction

The System Management Bus (SMBus) is a two-wire serial interface through which various system component chips can communicate with the master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the Master to all of the Slave devices on the bus. SDA is a bidirectional data signal between the Master and Slave devices. The LMH1218 SMBUS SCL and SDA signals are open drain and require external pull up resistors.

Start and Stop:

The Master generates Start and Stop conditions at the beginning and end of each transaction.

• Start: High to low transition (falling edge) of SDA while SCL is high
• Stop: Low to high transition (rising edge) of SDA while SCL is high

Figure 9. Start and Stop Conditions

The Master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the device pulls SDA low, while a NACK is recorded if the line remains high.

Figure 10. Acknowledge (ACK)

Writing data from a master to a slave comprises of 3 parts as noted in figure Figure 11

• The master begins with start condition followed by the slave device address with the R/W bit cleared
• The 8-bit register address that will be written
• The data byte to write

SMBus read operation consists of four parts

• The master initiates the read cycle with start condition followed by slave device address with the R/W bit cleared
• The 8-bit register address that is to be read
• After acknowledgment from the slave, the master initiates a re-start condition
• The slave device address is resent followed with R/W bit set
• After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is high if there are no more bytes to read

Figure 12. SMBus Read Operation

Figure 13. SMBus Timing Parameters