JAJSFM3E February 2015 – June 2018 LMH1218
PRODUCTION DATA.
REGISTER NAME | BITS | FIELD REGISTER ADDRESS | DEFAULT | R/RW | DESCRIPTION |
---|---|---|---|---|---|
SMBus Observation | Reg_0x00 Share | 0x00 | SMBus Address Observation | ||
7 | SMBUS_addr3 | 0 | R | SMBus strap observation | |
6 | SMBUS_addr2 | 0 | R | ||
5 | SMBUS_addr1 | 0 | R | ||
4 | SMBUS_addr0 | 0 | R | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Reserved | 0 | RW | ||
Reset Shared Regs | Reg 0x04 Share | 0x01 | Shared Register Reset | ||
7 | Reserved | 0 | RW | ||
6 | rst_i2c_regs | 0 | RW | 1: Reset Shared Registers
0: Normal operation |
|
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | Reserved | 0 | RW | ||
0 | Reserved | 1 | RW | ||
Enable SMBus Strap | Reg 0x06 Share | 0x00 | Allow SMBus strap observation | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | Test control[3] | 0 | RW | Set to >9 to allow strap observation on share reg 0x00 | |
2 | Test control[2] | 0 | RW | ||
1 | Test control[1] | 0 | RW | ||
0 | Test control[0] | 0 | RW | ||
Device Version | Reg 0xF0 Share | 0x01 | Device Version | ||
7 | VERSION[7] | 0 | RW | Device revision | |
6 | VERSION[6] | 0 | RW | ||
5 | VERSION[5] | 0 | RW | ||
4 | VERSION[4] | 0 | RW | ||
3 | VERSION[3] | 0 | RW | ||
2 | VERSION[2] | 0 | RW | ||
1 | VERSION[1] | 0 | RW | ||
0 | VERSION[0] | 1 | RW | ||
Device ID | Reg 0xF1 Share | 0x60 | Device ID | ||
7 | DEVICE_ID[7] | 0 | RW | Device ID | |
6 | DEVICE_ID[6] | 1 | RW | ||
5 | DEVICE_ID[5] | 1 | RW | ||
4 | DEVICE_ID[4] | 0 | RW | ||
3 | DEVICE_ID[3] | 0 | RW | ||
2 | DEVICE_ID[2] | 0 | RW | ||
1 | DEVICE_ID[1] | 0 | RW | ||
0 | DEVICE_ID[0] | 0 | RW | ||
Channel Control | Reg 0xFF Control | 0x00 | Enable Channel Control | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | los_int_bus_sel | 0 | RW | 1: Selects interrupt onto LOS pin
0: Select signal detect onto LOS pin |
|
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | en_ch_Access | 0 | RW | 1: Enables access to channel registers
0: Enable access to share register |
|
1 | Reserved | 0 | RW | ||
0 | Reserved | 0 | RW | ||
Reset_Channel_Regs | Reg_0x00 Channel | 0x00 | Reset all Channel Registers to Default Values | ||
7 | Reserved | 0 | |||
6 | Reserved | 0 | |||
5 | Reserved | 0 | |||
4 | Reserved | 0 | |||
3 | Reserved | 0 | |||
2 | Rst_regs | 0 | 1: Reset Channel Registers ( self clearing )
0: Normal operation |
||
1 | Reserved | 0 | |||
0 | Reserved | 0 | |||
LOS_status | Reg_0x01 Channel | 0x00 | Signal Detect Status | ||
7 | Reserved | 0 | RW | ||
6 | Reserved | 0 | RW | ||
5 | Reserved | 0 | RW | ||
4 | Reserved | 0 | RW | ||
3 | Reserved | 0 | RW | ||
2 | Reserved | 0 | RW | ||
1 | LOS1 | 0 | R | 1: Loss of signal on IN1
0: Signal present on IN1 |
|
0 | LOS0 | 0 | R | 1: Loss of signal on IN0
0: Signal present on IN0 |
|
CDR_Status_1 | Reg_0x02 Channel | 0x00 | CDR Status | ||
7 | Reserved | 0 | R | ||
6 | Reserved | 0 | R | ||
5 | Reserved | 0 | R | ||
4 | cdr_status[4] | 0 | R | 11: CDR locked
00: CDR not locked |
|
3 | cdr_status[3] | 0 | R | ||
2 | Reserved | 0 | R | ||
1 | Reserved | 0 | R | ||
0 | Reserved | 0 | R | ||
Interrupt Status Register | Reg 0x54 Channel | 0x00 | Interrupt Status ( clears upon read ) | ||
7 | Sigdet | 0 | R | 1: Signal Detect from the selected input asserted
0: Signal Detect from the selected input de-asserted |
|
6 | cdr_lock_int | 0 | R | 1: CDR Lock interrupt
0: No interrupt from CDR Lock |
|
5 | signal_det1_int | 0 | R | 1: IN1 Signal Detect interrupt
0: No interrupt from IN1 Signal Detect |
|
4 | signal_det0_int | 0 | R | 1: IN0 Signal Detect interrupt
0: No interrupt from IN0 Signal Detect |
|
3 | heo_veo_int | 0 | R | 1: HEO_VEO Threshold reached interrupt
0: No interrupt from HEO_VEO |
|
2 | cdr_lock_loss_int | 0 | R | 1: CDR loss of lock interrupt
0: No interrupt from CDR lock |
|
1 | signal_det1_loss_int | 0 | R | 1: IN1 Signal Detect loss interrupt
0: No interrupt from IN1 Signal Detect |
|
0 | signal_det0_loss_int | 0 | R | 1: IN0 Signal Detect loss interrupt
0: No interrupt from IN0 Signal Detect |
|
Interrupt Control | Reg 0x56 Channel | 0x00 | Interrupt Mask | ||
7 | Reserved | 0 | RW | ||
6 | cdr_lock_int_en | 0 | RW | 1: Enable Interrupt if CDR lock is achieved
0: Disable interrupt if CDR lock is achieved |
|
5 | signal_det1_int_en | 0 | RW | 1: Enable interrupt if IN1 Signal Detect is asserted
0: Disable interrupt if IN1 Signal Detect is asserted |
|
4 | signal_det0_int_en | 0 | RW | 1: Enable interrupt if IN0 Signal Detect is asserted
0: Disable interrupt if IN0 Signal Detect is asserted |
|
3 | heo_veo_int_en | 0 | RW | 1: Enable interrupt if HEO-VEO threshold is reached
0: Disable interrupt due to HEO-VEO threshold |
|
2 | cdr_lock_loss_int_en | 0 | RW | 1: Enable interrupt if CDR loses lock
0: Disable interrupt if CDR loses lock |
|
1 | signal_det1_loss_int_en | 0 | RW | 1: Enable interrupt if there is loss of signal on IN1
0: Disable interrupt if there is loss of signal on IN1 |
|
0 | signal_det0_loss_int_en | 0 | RW | 1: Enable interrupt if there is loss of signal on IN0
0: Disable interrupt if there is loss of signal on IN0 |