JAJSI48C
March 2017 – October 2019
LMH1228
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
ブロック概略図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Recommended SMBus Interface Timing Specifications
6.7
Serial Parallel Interface (SPI) Timing Specifications
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
4-Level Input Pins and Thresholds
7.3.2
OUT0_SEL and SDI_OUT2_SEL Control
7.3.3
Input Signal Detect
7.3.4
Continuous Time Linear Equalizer (CTLE)
7.3.5
Clock and Data (CDR) Recovery
7.3.6
Internal Eye Opening Monitor (EOM)
7.3.7
Output Function Control
7.3.8
Output Driver Control
7.3.8.1
Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)
7.3.8.1.1
Output Amplitude (VOD)
7.3.8.1.2
Output Pre-Emphasis
7.3.8.1.3
Output Slew Rate
7.3.8.1.4
Output Polarity Inversion
7.3.8.2
Host-Side 100-Ω Output Driver (OUT0±)
7.3.9
Status Indicators and Interrupts
7.3.9.1
LOCK_N (Lock Indicator)
7.3.9.2
SD_N (Signal Detect)
7.3.9.3
INT_N (Interrupt)
7.4
Device Functional Modes
7.4.1
System Management Bus (SMBus) Mode
7.4.1.1
SMBus Read and Write Transaction
7.4.1.1.1
SMBus Write Operation Format
7.4.1.1.2
SMBus Read Operation Format
7.4.2
Serial Peripheral Interface (SPI) Mode
7.4.2.1
SPI Read and Write Transactions
7.4.2.2
SPI Write Transaction Format
7.4.2.3
SPI Read Transaction Format
7.4.2.4
SPI Daisy Chain
7.5
Register Maps
8
Application and Implementation
8.1
Application Information
8.1.1
SMPTE Requirements and Specifications
8.1.2
Low-Power Optimization
8.1.3
Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
8.2
Typical Applications
8.2.1
Dual Cable Driver
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
Distribution Amplifier
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Board Stack-Up and Ground References
10.1.2
High-Speed PCB Trace Routing and Coupling
10.1.2.1
SDI_OUT1± and SDI_OUT2±:
10.1.2.2
IN0± and OUT0±:
10.1.3
Anti-Pads
10.1.4
BNC Connector Layout and Routing
10.1.5
Power Supply and Ground Connections
10.1.6
Footprint Recommendations
10.2
Layout Example
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントのサポート
11.1.1
関連資料
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
商標
11.5
静電気放電に関する注意事項
11.6
輸出管理に関する注意事項
11.7
Glossary
12
メカニカル、パッケージ、および注文情報
12.1
Package Option Addendum
12.1.1
Packaging Information
12.1.2
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTV|32
MPQF166B
サーマルパッド・メカニカル・データ
RTV|32
QFND101J
発注情報
jajsi48c_oa
jajsi48c_pm
7.3.8
Output Driver Control