JAJSJ18A June 2024 – October 2024 LMH1229 , LMH1239
PRODUCTION DATA
SMBus is a two-wire serial interface through which various system component chips can communicate with the controller. Target devices are identified by having a unique device address. The two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the controller to all of the target devices on the bus. SDA is a bidirectional data signal between the controller and target devices. The LMH12x9 SMBus SCL and SDA signals are open-drain and require external pullup resistors.
Start and Stop:
The controller generates Start and Stop patterns at the beginning and end of each transaction.
The controller generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device pulls SDA low, while a NACK is recorded if the line remains high.