JAJSJ18A June 2024 – October 2024 LMH1229 , LMH1239
PRODUCTION DATA
For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on the rising edge of CS_N. The SPI transaction always starts on the rising edge of the clock.
The signal timing for a SPI Write transaction is shown in Figure 6-7. The prime values on POCI (for example, A7') reflect the contents of the shift register from the previous SPI transaction and are do not care for the current transaction.