The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.
The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.
The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH1983 | WQFN (40) | 6.00 mm × 6.00 mm |
Changes from H Revision (October 2014) to I Revision
Changes from G Revision (Nov 2012) to H Revision
When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize to a previous reference with glitch-less operation.
PIN | I/O | SIGNAL LEVEL |
DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1 | VDD | – | Power | 3.3-V supply for PLL1 |
2 | VDD | – | Power | 3.3-V supply for logic I/O |
3 | Hin | I | LVCMOS | Horizontal sync reference signal Auto polarity correction for HVF will be based off Hin polarity. Recognized clock inputs can be applied to Hin. |
4 | Vin | I | LVCMOS | Vertical sync reference signal |
5 | Fin | I | LVCMOS | Field sync (odd/even) reference signal |
6 | INIT | I | LVCMOS | Reset signal for audio-video phase alignment (rising edge triggered) |
7 | ADDR | I | LVCMOS | I2C address select Pin settings: – Tie low: 0x65 (7-bit slave address in hex) – Float: 0x66 – Tie high: 0x67 |
8 | SDA(1) | I/O | I2C | I2C Data signal |
9 | SCL(1) | I | I2C | I2C Clock signal |
10 | VDD | – | Power | 3.3-V supply for logic I/O |
11 | NO_LOCK(2) | O | LVCMOS | Loss of lock status flag for PLLs 1-4 (active high) |
12 | NO_ALIGN | O | LVCMOS | Loss of alignment status flag for OUTs 1–4 (active high) |
13 | NO_REF | O | LVCMOS | Loss of reference status flag (active high) |
14 15 |
CLKout4– CLKout4+ |
O | LVDS | Audio clock from PLL4 (fundamental rate is 98.304 MHz). The output is 24.576 MHz by default and is selectable via the host. |
16 | VDD | – | Power | 3.3 V supply for CLKout4 |
17 | Fout4 (OSCin) | I/O | LVCMOS | Audio frame timing signal for OUT4 (active low.) Timing Generator fixed to PLL4 clock. The output is the audio-video-frame (AVF) pulse by default and is programmable via the host. Optional OSCin function can be used to apply a 27 MHz external clock for PLL4 to generate an audio clock independent of the video input reference; this function must be enabled via the host. |
18 | GND | – | GND | Ground |
19 | VDD | – | Power | 3.3 V supply for PLL3 and PLL4 |
20 | VDD | – | Power | 3.3 V supply for CLKout3 |
21 | GND | – | GND | Ground |
22 | Fout3 | O | LVCMOS | Video frame timing signal for OUT3 (active low). Timing generator assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable via the host. |
23 24 |
CLKout3+ CLKout3– |
O | LVDS | Video clock from PLL1, PLL2, or PLL3 depending on output crosspoint mode. The output is 148.35 MHz by default and is selectable via the host. |
25 | Cbyp3 | – | Analog | Bias bypass for on-chip LDO for PLL3 Connect to 1.0 µF and 0.1 µF bypass capacitors. |
26 | Cbyp4 | – | Analog | Bias bypass for on-chip LDO for PLL4 Connect to 1.0 µF and 0.1 µF bypass capacitors. |
27 | Cbyp2 | – | Analog | Bias bypass for on-chip LDO for PLL2 Connect to 1.0 µF and 0.1 µF bypass capacitors. |
28 29 |
CLKout2+ CLKout2– |
O | LVDS | Video clock from PLL1, PLL2, or PLL3 depending on output crosspoint mode. The output is 148.5 MHz by default and is selectable via the host. |
30 | Fout2 | O | LVCMOS | Video frame timing signal for OUT2 (active low). Timing generator assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable via the host. |
31 | VDD | – | Power | 3.3-V supply for CLKout2 |
32 | VDD | – | Power | 3.3-V supply for PLL2 |
33 34 |
XOin–(3)
XOin+ |
I | LVCMOS/LVDS | 27 MHz VCXO clock signal for PLL1. – LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to mid-supply with 0.1µF bypass capacitor. – LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.(4) |
35 36 |
CLKout1– CLKout1+ |
O | LVDS | Video clock from PLL1. The output is 27 MHz by default and is selectable via the host. |
37 | Fout1 | O | LVCMOS | Reference frame timing signal for OUT1 (active Low). Timing generator fixed to PLL1 OUT1 Format follows the reference input format. |
38 | VDD | – | Power | 3.3 V supply for CLKout1 |
39 | GND | – | GND | Ground |
40 | VC_LPF | O | Analog | Loop filter for PLL1 charge pump output with VCXO Voltage Control (VC) sensing. If free-run and holdover mode, PLL1 is disabled and an internal DAC outputs a control voltage to the VCXO. |
– | DAP | – | GND | Die Attach Pad (Connect to ground on PCB) |