JAJSQ78A april   2023  – august 2023 LMH32401-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Gain = 2 kΩ
    6. 6.6 Electrical Characteristics: Gain = 20 kΩ
    7. 6.7 Electrical Characteristics: Both Gains
    8. 6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switched Gain Transimpedance Amplifier
      2. 7.3.2 Clamping and Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Power-Down Mode (Multiplexer Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230413-SS0I-RCBB-853D-QH0VLGT8MNSR-low.svg Figure 5-1 RGT Package, 16-Pin VQFN With Wettable Flanks and Exposed Thermal Pad (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
EN 6 Input Device enable pin.
EN = logic low = normal operation (default)(1).
EN = logic high = power-off mode.
GAIN 16 Input Gain setting.
GAIN = low = 2 kΩ (default)(1).
GAIN = high = 20 kΩ.
GND 1, 7 Input Amplifier ground
IDC_EN 5 Input Ambient light cancellation (ALC) loop enable.
IDC_EN = logic low = enable dc current cancellation (default)(1).
IDC_EN = logic high = disable dc current cancellation.
IN 3 Input Transimpedance amplifier input
NC 4, 8, 13, 15 — Do not connect
OUT– 11 Output Inverting amplifier output. When light is incident on the photodiode, the output pin transitions in a negative direction from the no-light condition (APD anode connected to negative bias).
OUT+ 10 Output Noninverting amplifier output. When light is incident on the photodiode, the output pin transitions in a positive direction from the no-light condition (APD anode connected to negative bias).
VDD1 2 Input Positive power supply for the transimpedance amplifier stage
VDD2 14 Input Positive power supply for the differential amplifier stage. Tie VDD1 and VDD2 to the same power supply with independent power-supply bypassing.
VOCM 12 Input Differential-amplifier common-mode output setting
VOD 9 Input Differential-amplifier differential output offset setting
Thermal pad Thermal pad — Connect the thermal pad to GND or the most negative power supply of the device under test (DUT).
(1) Drive a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients can couple into the pin and inadvertently change the logic level.