JAJSQ78A april   2023  – august 2023 LMH32401-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Gain = 2 kΩ
    6. 6.6 Electrical Characteristics: Gain = 20 kΩ
    7. 6.7 Electrical Characteristics: Both Gains
    8. 6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switched Gain Transimpedance Amplifier
      2. 7.3.2 Clamping and Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Power-Down Mode (Multiplexer Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 Power-Down Mode (Multiplexer Mode)

To place the LMH32401-Q1 into a power-down mode, and thus help save system power, set EN high. Power-down mode puts the outputs of the LMH32401-Q1 internal amplifiers, including the differential outputs, into a high-impedance state. If a system consists of several photodiode and amplifier channels multiplexed to a single ADC channel, Figure 7-3 shows how this device feature can further save board space and cost by eliminating the need for a discrete high-speed multiplexer. The disabled channel outputs are not an ideal open circuit; therefore, as the number of multiplexed channels increases, the disabled channels begin to load the enabled channel. Multiplexing more than four channels in parallel degrades the performance of the enabled channel. When the amplifier is in power-down mode, the clamp circuitry is still active, thereby protecting the TIA input. The ALC loop is disabled when the amplifier is placed in power-down mode. When the LMH32401-Q1 is brought out of power-down operation, the ALC loop requires several time constants to settle. Figure 6-9 shows the low-frequency loop response, which in turn determines the time constant required for the loop to settle.

GUID-20230418-SS0I-J3LK-LXBM-3H3VDQFFZL51-low.svg Figure 7-3 Configuring Two LMH32401-Q1 Devices in Multiplexer Mode to Drive a Single ADC