JAJSLZ9A December   2021  – November 2022 LMH5485-SEP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Vs+ – Vs- = 5 V
    6. 7.6 Electrical Characteristics: Vs+ – Vs- = 3 V
    7. 7.7 Typical Characteristics: 5 V Single Supply
    8. 7.8 Typical Characteristics: 3 V Single Supply
    9. 7.9 Typical Characteristics: 3 V to 5 V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

7.9 Typical Characteristics: 3 V to 5 V Supply Range

at Vs+ = 3 V and 5 V, Vs– = GND, VOCM is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≅ 25°C (unless otherwise noted)

Figure 7-9 Main Amplifier Differential Open-Loop Gain and Phase vs Frequency
Figure 7-11 Input Spot Noise Over Frequency
GUID-4840AAC5-E731-42D5-96CF-7DAEBF86CF0D-low.gif
Common-mode in to differential out, gain of 2 simulation
Figure 7-13 CMRR Over Frequency
GUID-E5E05F62-AE81-4EA4-9D51-E9101BD0B2FA-low.gif
VOCM input either driven to mid-supply by low impedance source, or allowed to float and default to mid-supply
Figure 7-15 Output Common-Mode Noise
GUID-AA10FD97-CA54-4E74-AEC4-AB2A0954C182-low.gif
Single-ended to differential gain of 2 (see Figure 8-1), PSRR for negative supply to differential output (1-kHz simulation)
Figure 7-17 –PSRR vs VOCM Approaching Vs–
Total of 1281 units for each supply. For Vs = 5 V: μ = 34.1 μV,
σ = 47.1 μV
Figure 7-19 Input Offset Voltage
Maximum differential output swing, VOCM at mid-supply
Figure 7-21 Differenital Output Voltage vs Rload
VOCM input floating. Total of 1281 units for each supply.
For Vs = 5 V: μ = 8.1 mV, σ = 4.3 mV
Figure 7-23 Common-Mode Output Offset from Vs+ / 2 Default Value
GUID-F41D9B85-1017-4F9D-BFD9-B4151ED4CFD5-low.gif
10 MHz, 1 VPP input single to differential gain of 2,
see Figure 8-2
Figure 7-25 PD Turn On Waveform
GUID-47722D23-6EAB-48F5-A4B5-036757B49D86-low.gif
Single-ended input to differential output, simulated differential output impedance, see Figure 8-1
Figure 7-10 Closed-Loop Output Impedance
GUID-2057E08F-E5F4-4F2F-9152-89DF04366FC3-low.gif
Single-ended input to differential output, gain of 2 (see Figure 8-1), simulated with 1% resistor, worst-case mismatch
Figure 7-12 Output Balance Error Over Frequency
GUID-8ADBBD2A-D860-4265-B9BC-3D1EEE887A63-low.gif
Single-ended to differential, gain of 2 (see Figure 8-1) PSRR simulated to differential output
Figure 7-14 PSRR Over Frequency
GUID-8A12B92A-0981-4D3A-A522-DDDC363F16EE-low.gif
Average VOCM output offset of 37 units, Standard deviation
< 2.5 mV, see Figure 8-2
Figure 7-16 VOCM Offset vs VOCM Setting
GUID-28170C09-59A8-4063-8FF3-921F1531AB81-low.gif
Single-ended to differential gain of 2 (see Figure 8-1), PSRR for positive supply to differential output (1-kHz simulation)
Figure 7-18 +PSRR vs VOCM Approaching Vs+
Total of 1281 units for each supply. For Vs = 5 V: μ = 7.0 nA,
σ = 35.9 nA
Figure 7-20 Input Offset Current
GUID-FDFE4C52-90D4-4F51-A8B7-D19D07EEC500-low.gif
Figure 7-22 Supply Current vs PD Voltage
Total of 1281 units for each supply. For Vs = 5 V: μ = 0.52 mV, σ = 1.4 mV
Figure 7-24 Common-Mode Output Offset from Driven VOCM
GUID-1E6E5556-F37A-4415-A2D1-591FCA5A5151-low.gif
10 MHz, 1 VPP input single to differential gain of 2,
see Figure 8-2
Figure 7-26 PD Turn Off Waveform