JAJSNR7E May   2008  – July 2024 LMH6518

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Preamplifier
        1. 6.3.1.1 Primary Output Amplifier
        2. 6.3.1.2 Auxiliary Amplifier
      2. 6.3.2 Overvoltage Clamp
      3. 6.3.3 Attenuator
      4. 6.3.4 Digital Control Block
    4. 6.4 Device Functional Modes
      1. 6.4.1 Primary Amplifier
      2. 6.4.2 Auxiliary Output
    5. 6.5 Programming
      1. 6.5.1 Logic Functions
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Oscilloscope Front End
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Settings and ADC SPI Code (ECM)
          2. 7.2.1.2.2 Input and Output Considerations
            1. 7.2.1.2.2.1 Output Swing, Clamping, and Operation Beyond Full Scale
          3. 7.2.1.2.3 Oscilloscope Trigger Applications
        3. 7.2.1.3 Application Curves
      2. 7.2.2 JFET LNA Implementation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Attenuator Design
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Unless otherwise noted, all limits are specified at TA = 25°C, input CM = 2.5 V, VCM = 1.2 V, VCM_Aux = 1.2 V, single-ended input drive, VCC = 5 V, VDD = 3.3 V, RL = 100-Ω differential (both main and auxiliary outputs), VOUT = 0.7 VPP differential (both main and auxiliary outputs), both main and auxiliary output specifications, full bandwidth setting, gain = 18.8 dB (preamp LG, 0-dB ladder attenuation), and full power setting (with auxiliary output turned on) (see Table 8-1 for abbreviations used).(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
DYNAMIC PERFORMANCE
LSBW –3-dB bandwidth All gains 900 MHz
Peaking All gains 1 dB
GF_0.1 dB ±0.1-dB gain flatness All gains 150 MHz
GF_1 dB ±1-dB gain flatness All gains 400 MHz
TRS Rise time 460 ps
TRL Fall time 450
OS Overshoot Main output 9%
ts_1 Settling time Main output, ±0.5% 10 ns
ts_2 Settling time Main output, ±0.05% 14
t_recover Recovery time(4) All gains <5 ns
PD Propagation delay VOUT = 0.7 VPP, all gains 1.2 ns
PD_VAR Propagation delay variation Gain varied 100 ps
NOISE, DISTORTION, AND RF SPECIFICATIONS
en_1 Input noise spectral density Max gain, 10 MHz 0.98 nV/√ Hz
en_2 Input noise spectral density Preamp LG and 0-dB ladder,
10 MHz		 4.1 nV/√ Hz
eno_1 RMS output noise Max gain, 100 Hz to 400 MHz 1.7 mV
eno_2 RMS output noise Preamp LG, 0-dB ladder,
100 Hz to 400 MHz		 940 µV
NF_1 Noise figure Max gain, RS = 50 Ω each input,
10 MHz		 3.8 dB
NF_2 Noise figure Preamp LG, 0-dB ladder,
RS = 50 Ω each input, 10 MHz		 13.5 dB
HD2_1 2nd harmonic distortion(5) Main output, 100 MHz, all gains –50 dBc
HD3_1 3rd harmonic distortion(5) Main output, 100 MHz, all gains –53 dBc
HD2_2 2nd harmonic distortion(5) Auxiliary output, 100 MHz, all gains –48 dBc
HD3_2 3rd harmonic distortion(5) Auxiliary output, 100 MHz, all gains –50 dBc
HD2_3 2nd harmonic distortion(5) Main output, 250 MHz, all gains –44 dBc
HD3_3 3rd harmonic distortion(5) Main output, 250 MHz, all gains –50 dBc
HD2/HD3_4 2nd and 3rd harmonic distortion(5) Auxiliary output, 250 MHz, all gains –42 dBc
IMD3 Intermodulation distortion(5) f = 250 MHz, main output –65 dBc
OIP3_1 Intermodulation intercept(5) Main output, 250 MHz 26 dBm
P_1dB_main –1-dB compression Main output, 250 MHz, 0-dB ladder 1.8 VPP
Main output, 250 MHz, 20-dB ladder 1
P_1dB_aux –1-dB compression Auxiliary output, 250 MHz,
0-dB ladder		 1.65 VPP
Auxiliary output, 250 MHz,
20-dB ladder		 1
GAIN PARAMETERS
AV_DIFF_MAX Maximum gain 38.1 38.8 39.5 dB
AV_DIFF_MIN Minimum gain –1.91 –1.16 –0.4 dB
Gain_Step Gain step size All gains including preamp step 1.8 2 2.2 dB
Gain step size with ADC
(see Section 7)		 ADC FS adjusted 8.5 mdB
Gain_Range Gain range 39 40 41 dB
TC_AV_DIFF Gain temp coefficient(6) All gains –0.8 mdB/°C
Gain_ACC Absolute gain accuracy Compared to theoretical from
max gain in 2-dB steps		 0.75 0.75 dB
MATCHING
Gain_match Gain matching,
main and auxiliary		 All gains ±0.1 ±0.2 dB
BW_match –3-dB bandwidth matching,
main and auxiliary		 All gains 5%
RT_match Rise time matching,
main and auxiliary		 All gains 5%
PD_match Propagation delay matching,
main and auxiliary		 All gains 100 ps
ANALOG I/O
CMRR_1 CM rejection ratio (see Table 8-1) Preamp HG, 0-dB ladder,
1.9 V < CMVR < 3.1 V		 45 86 dB
CMRR_2 CM rejection ratio (see Table 8-1) Preamp LG, 0-dB ladder,
1.9 V < CMVR < 3.1 V		 40 55 dB
CMVR_1 Input common-mode voltage Preamp HG, all ladder steps,
CMRR ≥ 45 dB		 1.9 3.1 V
CMVR_2 Input common-mode voltage Preamp LG, all ladder steps,
CMRR ≥ 40 dB		 1.9 3.1 V
|ΔVO_CM|ΔI_CM| All gains, 2 V < CMVR < 3 V –60 –100 dB
CMRR_CM CM rejection ratio relative to VCM (see Table 8-1) Preamp LG, 0 dB 101 dB
Zin_diff Differential input impedance All gains 150 || 1.5 kΩ || pF
Zin_CM CM input impedance Preamp HG 420 || 1.7 kΩ || pF
Preamp LG 900 || 1.7
FSOUT1 Full scale voltage swing Main output, all gains,
THD at 100 MHz ≤ –40 dBc		 770(7) 800 mVPP
FSOUT2 Full scale voltage swing Main output, clamped, 0‑dB ladder 1800 1960 mVPP
FSOUT3 Full scale voltage swing Auxiliary output, all gains
THD at 100 MHz ≤ –40 dBc		 770(7) 800 mVPP
FSOUT4 Full scale voltage swing Auxiliary output, clamped, 0-dB ladder 1600 1760 mVPP
VOUT_MAX1 Voltage at each
output pin (clamped)		 Main output, all gains, VCM = 1.2 V 0.5 1.8 V
VOUT_MAX2 Voltage at each
output pin (clamped)		 Auxiliary output, all gains,
VCM = 1.2 V		 0.8 2.2 V
VOUT_MAX3 Voltage at each
output pin (clamped)		 Main output, all gains, VCM = 1.45 V 2.05 V
VOUT_MAX4 Voltage at each
output pin (clamped)		 Auxiliary output, all gains,
VCM = 1.45 V		 2.45 V
ZOUT_DIFF Differential output impedance All gains 92 100 108 Ω
VOOS Output offset voltage All gains ±15 ±40 mV
VOOS_shift1 Output offset voltage shift Preamp LG to preamp HG 13.7 mV
VOOS_shift2 Output offset voltage shift All gains, excluding preamp step 12.7 mV
TCVOOS Output offset voltage drift(6) Preamp HG, 0-dB ladder –24 µV/°C
Preamp LG, 0-dB ladder –7
IB Input bias current(8) TA = –40°C to +85°C 40 100 µA
TA = –65°C to +150°C 140
VOCM Output CM voltage All gains TA = –40°C to +85°C 1.2 V
TA = –65°C to +150°C 0.95 1.45
VOS_CM Output CM offset All gains ±15 ±30 mV
TC_VOS_CM CM offset voltage
temperature coefficient		 All gains +55 µV/°C
BAL_Error_DC Output gain balance error
LMH6518
–78 dB
BAL_Error_AC Output gain balance error
LMH6518
–45 dB
PB Phase balance error (see Table 8-1) 250 MHz ±0.8 deg
PSRR Differential power-supply rejection (see Table 8-1) Preamp HG, 0-dB ladder –60 –87 dB
Preamp LG, 0-dB ladder –50 –70
PSRR_CM CM power-supply rejection (see Table 8-1) Preamp LG, 0-dB ladder –55 –71 dB
VCM_I VCM input bias current(8) All gains TA = –40°C to +85°C ±1 ±10 nA
TA = –65°C to +150°C ±20
VCM_AUX_I VCM_AUX input bias current(8) All gains TA = –40°C to +85°C ±1 ±10 nA
TA = –65°C to +150°C ±20
DIGITAL I/O
VIH Input logic high TA = –65°C to +150°C VDD – 0.6 V
VIL Input logic low TA = –65°C to +150°C 0.5 V
VOH Output logic high VDD V
VOL Output logic low 0 V
RHi_Z Output resistance High-impedance mode 5 MΩ
I_in Input bias current <1 µA
FSCLK SCLK rate 10 MHz
FSCLK_DT SCLK duty cycle 45% 50% 55%
POWER REQUIREMENTS
IS1 Supply current, VCC TA = –40°C to +85°C 195 210 225 mA
TA = –65°C to +150°C 230
IS1_off Supply current, VCC aux off TA = –40°C to +85°C 150 165 mA
TA = –65°C to +150°C 170
IDD Supply current, VDD TA = –40°C to +85°C 180 350 µA
TA = –65°C to 150°C 400
BANDWIDTH LIMITING FILTER SPECIFICATIONS
Pass band tolerance,
–3 dB bandwidth		 All gains 20 MHz 0% 20%
100 MHz 0% 20%
200 MHz 0% 20%
350 MHz ±25%
650 MHz ±25%
750 MHz ±25%
Preamp LG,
0-dB ladder		 350 MHz ±10%
650 MHz ±10%
750 MHz ±10%
(1) Electrical Characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C unless otherwise specified. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values can vary over time and also depends on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) Recovery time is the slower of the main and auxiliary outputs. Output swing of 700 mVPP shifted up or down by 50% (0.35 V) by introducing an offset. Measured values correspond to the time required to return to within ±1% of 0.7 VPP (±7 mV).
(5) Distortion data taken under single ended input condition.
(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Specified by design.
(8) Positive current is current flowing into the device.