12.1.1 Ground Planes

Solid ground planes are recommended as they provide a low-impedance return paths between the device and its bypass capacitors and its clock source and destination devices.

Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and so forth) from passing through the local ground of the device to minimize noise coupling, which could induce added jitter and spurious noise.

12.1.2 Power Supply Pins

Follow the power supply schematic and layout example described in Power-Supply Filtering.

12.1.3 Differential Input Termination

• Place input termination or biasing resistors as close as possible to the CLK/nCLK pins.
• Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities. Intra-pair skew should be also be minimized on the differential input traces.
• If not used, CLK/nCLK inputs may be left floating.

12.1.4 LVCMOS Input Termination

• When the LVCMOS_CLK input is driven from a LVCMOS driver that is series terminated to match the characteristic impedance of the trace, then input termination is not necessary; otherwise, place the input termination resistor as close as possible to the LVCMOS_CLK input.
• Avoid or minimize vias in the 50 Ω input trace to minimize impedance discontinuities.
• If not used, LVCMOS_CLK input may be left floating.

12.1.5 Output Termination

• Place 43 Ω series termination resistors as close as possible to the Qx outputs at the launch of the 50 Ω traces.
• Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities.
• If not used, any Qx output should be left floating and not routed.