JAJSSR6 January   2024 LMK5C33216AS1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
    2. 6.2 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL
        1. 7.2.2.1 Independent DPLL Operation
        2. 7.2.2.2 Cascaded DPLL Operation
        3. 7.2.2.3 APLL Cascaded with DPLL
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO)
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With Phase Cancellation
        2. 7.3.5.2 Hitless Switching With Phase Slew Control
        3. 7.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Frequency Monitoring
          3. 7.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
          1. 7.3.8.1.1 APLL Phase Detector Frequency
          2. 7.3.8.1.2 APLL VCO Frequency
          3. 7.3.8.1.3 DPLL TDC Frequency
          4. 7.3.8.1.4 DPLL VCO Frequency
          5. 7.3.8.1.5 Clock Output Frequency
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL XO Reference (R) Divider
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 7.3.8.7  APLL Voltage-Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 SYSREF/1-PPS
      13. 7.3.13 Output Delay
      14. 7.3.14 Clock Outputs (OUTx_P/N)
        1. 7.3.14.1 Differential Output
        2. 7.3.14.2 LVCMOS Output
        3. 7.3.14.3 SYSREF/1-PPS Output Replication
        4. 7.3.14.4 Output Auto-Mute During LOL
      15. 7.3.15 Glitchless Output Clock Start-Up
      16. 7.3.16 Clock Output Interfacing and Termination
      17. 7.3.17 Output Synchronization (SYNC)
      18. 7.3.18 Zero-Delay Mode (ZDM)
      19. 7.3.19 Time Elapsed Counter (TEC)
        1. 7.3.19.1 Configuring TEC Functionality
        2. 7.3.19.2 SPI as a Trigger Source
        3. 7.3.19.3 GPIO Pin as a TEC Trigger Source
          1. 7.3.19.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 7.3.19.4 TEC Timing
        5. 7.3.19.5 Other TEC Behavior
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up
        1. 7.4.1.1 ROM Selection
        2. 7.4.1.2 EEPROM Overlay
      2. 7.4.2 DPLL Operating States
        1. 7.4.2.1 Free-Run
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 DPLL Locked
        4. 7.4.2.4 Holdover
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 7.4.4.1 DPLL DCO Control
          1. 7.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 7.4.4.1.2 APLL DCO Frequency Step Size
      5. 7.4.5 APLL Frequency Control
      6. 7.4.6 DPLL Programmable Phase Delay
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Interface
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Interface
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map Generation
      5. 7.5.5 General Register Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PD#) Pin
      3. 8.1.3 Strap Pins for Start-Up
      4. 8.1.4 Pin States
      5. 8.1.5 ROM and EEPROM
      6. 8.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.6.1 Power-On Reset (POR) Circuit
        2. 8.1.6.2 Powering Up From a Single-Supply Rail
        3. 8.1.6.3 Power Up From Split-Supply Rails
        4. 8.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 8.1.7 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Clock Tree Architect Programming Software
        2. 9.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 9.1.1.3 PLLatinum™ Simulation Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5.2 Hitless Switching With Phase Slew Control

Enabling Phase Slew Control will constrain the output phase transient or phase hit during hitless switching and holdover exit. Users can select DPLLx_PHS1_EN to enable Phase Slew Control to follow the step limits set in DPLLx_PHS1_THRESH and DPLLx_PHS1_TIMER. When during hitless switching it is desired to transition slowly to tracking the new input phase, enabling phase slew control will remove the phase cancellation or phase build out based on the programmed timer value and step limits. Similarly when the DPLL switches from APLL-only mode or holdover mode to DPLL Lock Acquisition mode, or hitless switching with two inputs are not frequency-locked the phase slew limits would then be applied. When both Phase Cancellation function and Phase Slew Control function are disabled, a phase hit equal to the phase offset between XO and selected input or between the two inputs at the moment of switching will be propagated to the output at a rate determined by the DPLL loop bandwidth. In the case where two inputs are switched but are not frequency-locked Phase Slew Control function can ensure the output smoothly transitions to the new frequency as the rate the defined by the step limits.