Figure 8-6 shows APLL1 and APLL2 cascaded from the BAW APLL. The VCBO is held around the nominal center frequency of 2457.6MHz while APLL1 and APLL2 acquire lock. Subsequently, the BAW APLL locks the VCBO frequency to the external XO input and operates in free-run mode until a valid reference input is detected.

Cascaded PLLs lock to a divided frequency from the source VCO. When a valid DPLL reference input is detected beyond a minimum valid time, the DPLLs begin lock acquisition to the reference input. Each DPLL TDC compares the phase of the selected reference input clock and the FB divider clock from the respective VCO and generates a digital correction word corresponding to the phase error. At the beginning, the DPLL TDC simply cancels out the phase error with the no filtering correction word. Then, the subsequent correction word is filtered by the DLF, and the DLF output controls the APLL N divider SDM to pull the VCO frequency into lock with the reference input.

Using the VCBO as a cascade source to APLL1 or APLL2 provides the APLL a high-frequency, ultra-low-jitter reference clock. This unique cascading feature can provide improved close in phase noise performance if the XO/TCXO/OCXO is a low frequency or has poor phase noise performance. Note that in cascaded DPLL operation the best jitter performance and frequency stability is achieved after DPLL3 locked.

DPLL3 lock status impacts the other DPLLx lock status when DPLL3 is cascaded to the other DPLLx or APLLx. If the BAW APLL is in free-run mode or holdover mode, the VCBO frequency offset ppm value can introduce a similar frequency offset to the APLLx outputs even though the cascaded DPLLx remains in a locked status. In this configuration example, the best practice is to monitor the lock status of both the BAW APLL and the other APLLx. Alternatively at start-up, verify that the DPLL3 and the BAW APLL are locked first; next, toggle the other APLLx enable (APLLx_EN bit = 0 → 1) to calibrate the VCOx; then, double check the APLLx lock status.

In the above example, the BAW APLL is the upstream APLL, while APLL1 and APLL2 are the downstream APLLs. If there are system start-up requirements on the clock sequencing, APLL1 or APLL2 can also be configured as the upstream APLL.

When cascading APLLs, the downstream APLL can use the DPLL or bypass and power down the DPLL depending on performance requirements. If the other DPLLx is disabled from the above APLL cascaded mode, then DPLL3-only cascade mode can be used. In this case, VCO1 or VCO2 can track the VCBO domain during DPLL3 lock acquisition and locked modes, which allows the user to synchronize the clock domain of the APLL1 or APLL2 to the DPLL3 reference input.

When a DPLL is disabled, the best practice is to use the 24-bit numerator and programmable 24-bit denominator instead of the fixed 40-bit denominator to eliminate frequency error from APLL reference to output.

Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL+APLL pair.

Figure 8-5 APLL Cascaded With DPLLs Enabled Example

Figure 8-6 APLL Cascaded With DPLLs Disabled Example