The loss-of-lock (LOL) status is available for APLL1, APLL2, APLL3, DPLL1, DPLL2, and DPLL3. The APLLs are monitored for loss-of-frequency lock only. The DPLL can be monitored for both loss-of-frequency lock (LOFL) and loss-of-phase lock (LOPL). The DPLL lock threshold and loss-of-lock threshold are programmable for both LOPL and LOFL detectors. In the case when APLL3 loss-of-frequency lock is selected, then DPLL3 is monitored for LOPL only. DPLL3 must be enabled for the digital monitoring of APLL3 VCBO lock detect.

The DPLL frequency lock detector will clear its LOFL flag when the DPLL's frequency error relative to the selected reference input is less than the lock ppm threshold. Otherwise, the lock detector will set the LOFL flag when the DPLL's frequency error is greater than the unlock ppm threshold. The ppm delta between the lock and unlock thresholds provides hysteresis to prevent the LOFL flag from toggling when the DPLL frequency error is crossing these thresholds.

The APLL3 frequency digital lock detector will clear its LOFL flag when the APLL3 VCBO frequency error relative to the XO reference input is less than the lock ppm threshold. Otherwise, the lock detector will set the LOFL flag when the VCBO's frequency error is greater than the unlock ppm threshold. Make sure to take the ppm frequency tolerance of the XO input reference into account when setting the VCBO frequency lock and unlock thresholds. The ppm delta between the lock and unlock thresholds provides hysteresis to prevent the LOFL flag from toggling when the VCBO frequency error is crossing these thresholds.

A measurement accuracy (ppm) and averaging factor are used in computing the frequency lock detector register settings. A higher measurement accuracy (smaller ppm) or higher averaging factor will increase the measurement delay to set or clear the LOFL flag. Higher averaging may be useful when locking to an input with high wander or when the PLL is configured with a narrow loop bandwidth. Note that higher averaging reduces the maximum frequency ppm thresholds that can be configured.

The DPLL phase lock detector will clear its LOPL flag when the phase error of the DPLL is less than the phase lock threshold. Otherwise, the lock detector will set the LOPL flag when the phase error is greater than the phase unlock threshold.

Users can observe the APLL and DPLL lock detector flags through the status pins and the status bits.

Figure 7-18 PLL Lock Detectors and History Monitor