JAJSLE1 December   2023 LMK5C33414A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
    2. 6.2 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL
        1. 7.2.2.1 Independent DPLL Operation
        2. 7.2.2.2 Cascaded DPLL Operation
        3. 7.2.2.3 APLL Cascaded with DPLL
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO)
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With Phase Cancellation
        2. 7.3.5.2 Hitless Switching With Phase Slew Control
        3. 7.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Frequency Monitoring
          3. 7.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
          1. 7.3.8.1.1 APLL Phase Detector Frequency
          2. 7.3.8.1.2 APLL VCO Frequency
          3. 7.3.8.1.3 DPLL TDC Frequency
          4. 7.3.8.1.4 DPLL VCO Frequency
          5. 7.3.8.1.5 Clock Output Frequency
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL XO Reference (R) Divider
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 7.3.8.7  APLL Voltage-Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 SYSREF/1-PPS
      13. 7.3.13 Output Delay
      14. 7.3.14 Clock Outputs (OUTx_P/N)
        1. 7.3.14.1 Differential Output
        2. 7.3.14.2 LVCMOS Output
        3. 7.3.14.3 SYSREF/1-PPS Output Replication
        4. 7.3.14.4 Output Auto-Mute During LOL
      15. 7.3.15 Glitchless Output Clock Start-Up
      16. 7.3.16 Clock Output Interfacing and Termination
      17. 7.3.17 Output Synchronization (SYNC)
      18. 7.3.18 Zero-Delay Mode (ZDM)
      19. 7.3.19 Time Elapsed Counter (TEC)
        1. 7.3.19.1 Configuring TEC Functionality
        2. 7.3.19.2 SPI as a Trigger Source
        3. 7.3.19.3 GPIO Pin as a TEC Trigger Source
          1. 7.3.19.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 7.3.19.4 TEC Timing
        5. 7.3.19.5 Other TEC Behavior
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up
        1. 7.4.1.1 ROM Selection
        2. 7.4.1.2 EEPROM Overlay
      2. 7.4.2 DPLL Operating States
        1. 7.4.2.1 Free-Run
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 DPLL Locked
        4. 7.4.2.4 Holdover
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 7.4.4.1 DPLL DCO Control
          1. 7.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 7.4.4.1.2 APLL DCO Frequency Step Size
      5. 7.4.5 APLL Frequency Control
      6. 7.4.6 DPLL Programmable Phase Delay
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Interface
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Interface
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map Generation
      5. 7.5.5 General Register Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PD#) Pin
      3. 8.1.3 Strap Pins for Start-Up
      4. 8.1.4 Pin States
      5. 8.1.5 ROM and EEPROM
      6. 8.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.6.1 Power-On Reset (POR) Circuit
        2. 8.1.6.2 Powering Up From a Single-Supply Rail
        3. 8.1.6.3 Power Up From Split-Supply Rails
        4. 8.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 8.1.7 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Clock Tree Architect Programming Software
        2. 9.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 9.1.1.3 PLLatinum™ Simulation Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 用語集
    7. 9.7 静電気放電に関する注意事項
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
IDD_TOT Total current consumption with specified configuration 245.76 MHz from OUT0 to OUT13, LVDS/HSDS 400 mV, APLL3 post-divider = 5, channel divider = 2, DPLL1/2 and APLL1/2 disabled 850 940 mA
245.76 MHz from OUT0 to OUT13, HSDS 800 mV, APLL3 post-divider = 5, channel divider = 2, DPLL1/2 and APLL1/2 disabled 965 1075 mA
100 MHz from OUT0 to OUT3 (APLL1), 312.5 MHz from OUT4 to OUT7 (APLL2), 491.52 MHz from OUT8 to OUT13 (APLL3), HSDS 800 mV, DPLL1/2/3 disabled 1085 1195 mA
IDD-XO XO input current consumption XO 3.5 mA
IDD-XO2X Current consumption per XO doubler XO doubler(1) 0.3 mA
IDD-INX Core current consumption per DPLL reference input block IN0 3.6 mA
IN1 3.1 mA
IN2 and IN3 5 mA
IDD-DPLL Current consumption per DPLL DPLL(2) 55 mA
IDD-APLL1 APLL1 current consumption APLL1  90 mA
IDD-APLL2 APLL2 current consumption APLL2  160 mA
IDD-APLL3 APLL3 current consumption APLL3  120 mA
IDD-ANA Analog bias current consumption Analog circuitry from VDD_APLL1_XO supply pin. Always on when device is enabled. 42 mA
IDD-DIG Digital control current consumption Digital control circuitry from VDD_DIG supply pin., Always on when device is enabled. 34 mA
IDDO-CHDIV Current consumption per channel divider block 12-bit channel divider 20 mA
IDDO-1PPSDIV Current consumption per 1-PPS/SYSREF divider block 20-bit 1-PPS/SYSREF divider 12 mA
IDDO-DELAY Current consumption per 1-PPS/SYSREF analog delay block Analog delay function enabled 10 mA
IDDO-HSDS HSDS current consumption per output driver HSDS buffer (VCM level = s1, Iout = 4 mA, 100-Ω termination)  19 mA
HSDS buffer (VCM level = s1, Iout = 7 mA, 100-Ω termination) 22 mA
HSDS buffer (VCM level = s1, Iout = 10 mA, 100-Ω termination) 25 mA
IDDO-HCSL HCSL current consumption per output driver HCSL output (50-Ω termination per side) 30.5 mA
IDD_PD Power-down current consumption Device powered-down, PD# = LOW 90 110 mA
Reference Input Characteristics (INx)
fIN INx frequency range Single-ended input 0.5E–6 200 MHz
Differential input 5 800
VIH Single-ended input high voltage DC-coupled input mode  (3) 1.2 VDD + 0.3 V
VIL Single-ended input low voltage 0.5 V
VIN-SE-PP Single-ended input voltage swing AC-coupled input mode (4) 0.4 2 Vpp
VIN-DIFF-PP Differential input voltage swing AC- or DC- coupled input (5) 0.4 2 Vpp
VICM Input Common Mode DC- coupled differential input (6) 0.1 2 V
dV/dt Input slew rate Single-ended input 0.2 0.5 V/ns
Differential input 0.2 0.5 V/ns
IDC Input Clock Duty Cycle Non 1-PPS signal 40 60 %
tPULSE-1PPS 1-PPS pulse width for input 1-PPS or pulsed signal 100 ns
IIN-DC DC input leakage current Single pin INx_P or INx_N, 50-Ω and 100-Ω internal terminations disabled, AC coupled mode enabled or disabled –350 350 µA
CIN Input capacitance Single-ended, each pin 2 pF
XO/TCXO Input Characteristics (XO)
fCLK XO input frequency range (7) 10 156.25 MHz
VIH LVCMOS Input high voltage DC-coupled input mode (8) 1.4 VDD + 0.3 V
VIL LVCMOS Input low voltage 0.8 V
VIN-SE Single-ended input voltage swing AC-coupled input mode (9) 0.4 VDD + 0.3 Vpp
dV/dt Input slew rate 0.2 0.5 V/ns
IDC Input duty cycle 40 60 %
IIN-DC DC Input leakage current Single pin XO_P, 50-Ω and 100-Ω internal terminations disabled –350 350 µA
CIN Input capacitance on each pin 1 pF
CEXT External AC coupling cap 10 nF
APLL/VCO Characteristics
fPFD PFD frequency range APLL3 Fractional feedback divider 110 MHz
APLL1, APLL2 Fractional feedback divider 125 MHz
fVCO1 VCO1 Frequency range 4800 5350 MHz
fVCO2 VCO2 Frequency range 5595 5950 MHz
fVCO3 VCO3 Frequency range 2433 2457.6 2482.2 MHz
tAPLL1-LOCK APLL1 lock time Time between soft or hard reset and stable APLL1 output. 20 35 ms
tAPLL2-LOCK APLL2 lock time Time between soft or hard reset and stable APLL2 output. 350 460 ms
tAPLL3-LOCK APLL3 lock time Time between soft or hard reset and stable APLL3 output. 12.5 13 ms
HSDS Output Characteristics (OUTx)
fOUT Output frequency range 1E–6 1250 MHz
VOUT-DIFF Differential output swing 2×VOD-HSDS mVpp
VOD-HSDS HSDS output voltage swing fout < 100 MHz, Iout = 4 mA  350 400 440 mV
fout < 100 MHz, Iout = 7 mA 625 700 750 mV
fout < 100 MHz, Iout = 10 mA 900 975 1050 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 4 mA 335 400 445 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 5 mA 425 500 575 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 6 mA 510 600 690 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 7 mA 595 700 805 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 8 mA 680 800 920 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 9 mA 765 900 1035 mV
100 MHz ≤ fout ≤ 325 MHz, Iout = 10 mA 850 1000 1150 mV
325 MHz < fout ≤ 800 MHz, Iout = 4 mA 300 350 400 mV
325 MHz < fout ≤ 800 MHz, Iout = 7 mA 580 640 700 mV
325 MHz < fout ≤ 800 MHz, Iout = 10 mA 800 865 940 mV
800 MHz < fout ≤ 1250 MHz, Iout = 4 mA 235 320 400 mV
800 MHz < fout ≤ 1250 MHz, Iout = 7 mA 480 625 740 mV
800 MHz < fout ≤ 1250 MHz, Iout = 10 mA 600 800 1000 mV
VOH Output voltage high VOL + VOD mVpp
VOL Output voltage low VCM level = s1 50 150 250 mV
VCM level = s2+3 300 470 720 mV
VCM Output common mode voltage VCM level = s1 or s2+3 VOL + VOD/2 V
VCM level = s2, Iout = 4 mA 0.6 0.7 0.8 V
VCM level = s3, Iout = 4 mA 1.125 1.25 1.375 V
tSKEW Output skew (12) Same APLL, same post divider and channel divider values, same bank 50 ps
Same APLL, same post divider and channel divider values, between banks 80 ps
tR/tF Rise/Fall time fOUT < 100 MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2 pF 200 250 350 ps
100 MHz ≤ fOUT ≤ 325 MHz, 20% to 80%, Iout ≥ 8 mA, OUT_x_CAP_EN = 0, CL = 2 pF 165 225 260 ps
100 MHz ≤ fOUT ≤ 325 MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2 pF 175 230 300 ps
325 MHz < fOUT ≤ 800 MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2 pF 150 215 285 ps
800 MHz < fOUT ≤ 1250 MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2 pF 120 205 250 ps
ODC Output duty cycle 48 52 %
HCSL Output Characteristics (OUTx)
fOUT Output frequency range HSCL output mode 25 100 650 MHz
VOL Output voltage low –150 0 150 mV
VOH Output voltage high 600 750 900 mV
VMIN Output voltage minimum Including undershoot –300 0 150 mV
VMAX Output voltage maximum Including overshoot 600 750 1150 mV
dV/dt Differential output slew rate ±150 mV around center point, OUT_x_CAP_EN = 1, CL= 2 pF 2 4 V/ns
dV/dt Differential output slew rate ±150 mV around center point,OUT_x_CAP_EN = 0, CL= 2 pF 3 5 V/ns
tSKEW Output skew (12) Same APLL, same post divider and channel divider values, same bank 50 ps
Same APLL, same post divider and channel divider values, between banks 80 ps
VCROSS Absolute voltage crossing point fOUT = 100 MHz 300 500 mV
ΔVCROSS Voltage crossing point variation fOUT = 100 MHz 75 mV
ODC Output duty cycle 45 55 %
1.8-V LVCMOS Output Characteristics (OUT0/1)
fOUT Output frequency range 1E–6 200 MHz
VOH Output high voltage IOH = -2 mA 1.5 V
VOL Output low voltage IOL = 2 mA 0.2 V
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew OUT0_P, OUT0_N, OUT1_P, OUT1_N with same polarity, same APLL post divider and output divider values. Same polarity and output type (LVCMOS) 60 ps
Same APLL, same post divider and output divider values. Skew between LVCMOS and differential outputs 0.7 1 1.3 ns
ODC Output duty cycle 45 55 %
ROUT Output impedance 54 64 75 Ω
2.65-V LVCMOS Output Characteristics (OUT0/1)
fOUT Output frequency range 1E–6 200 MHz
VOH Output high voltage IOH = -2 mA 2.3 V
VOL Output low voltage IOL = 2 mA 0.2 V
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew OUT_P, OUT0_N, OUT1_P, OUT1_N with same polarity, same APLL post divider and output divider values. Same polarity and output type (LVCMOS) 60 ps
Same APLL, same post divider and output divider values. Skew between LVCMOS and differential outputs 0.7 1.0 1.3 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 25 MHz –155 dBc/Hz
ODC Output duty cycle 45 55 %
ROUT Output impedance 40 50 65 Ω
3.3-V LVCMOS GPIO Clock Output Characteristics (GPIO0/1/2)
fOUT Maximum output frequency GPIO1, GPIO2  25 MHz
VOH Output high voltage IOH= 2 mA 2.4 V
VOL Output low voltage IOL= 2 mA 0.4 V
IIH Input high current VIN = VDD 100 µA
IIL Output low current VIN = 0V -100 µA
tR/tF Output rise/fall time 20% to 80%, 1 kΩ to GND 0.5 1.3 2.6 ns
tSK Output-to-output skew GPIO1, GPIO2 output skew compared to OUT0_P, OUT0_N, OUT1_P, OUT1_N CMOS outputs. GPIOx_SEL = 115
fout = 100 kHz		 7.5 11 ns
ODC Output duty cycle 45 55 %
ROUT Output impedance 35 42 50 Ω
PLL Output Clock Noise Characteristics
RJAPLL3 12 kHz to 20 MHz integrated RMS jitter for APLL3 outputs XO = 48 MHz, fout = 1222.8 MHz,  post divider P1APLL3 = 2, HSDS output  VOD ≥ 800 mV  45 fs
XO = 48 MHz, fout = 614.4 MHz,  post divider P1APLL3 = 4, HSDS output  VOD ≥ 800 mV 35 50 fs
XO = 48 MHz, fout = 491.52 MHz,  post divider P1APLL3 = 5,  HSDS output  VOD ≥ 800 mV  40 57 fs
XO = 48 MHz, fout = 245.76 MHz,  post divider  P1APLL3 = 10, HSDS output  VOD ≥ 800 mV 45 64 fs
XO = 48 MHz, fout = 245.76 MHz,  bypass post divider P1APLL3 = 1, HSDS output  VOD ≥ 800 mV (10) 50 62 fs
XO = 48 MHz, fout = 122.88 MHz,  bypass post divider P1APLL3 = 1, HSDS output  VOD ≥ 800 mV (10) 55 86 fs
XO = 48 MHz, fout = 245.76MHz, HSDS output, all VOD levels 50 80 fs
XO = 48 MHz, fout = 122.88 MHz, HSDS output, all VOD levels 60 90 fs
RJAPLL2 12 kHz to 20 MHz integrated RMS jitter for APLL2 outputs XO = 48 MHz, fout = 153.6 MHz (VCO2 = 5836.8 MHz), 155.52 MHz (VCO2 = 5598.72 MHz), 174.703084 MHz (VCO2 = 5765.2 MHz) or 184.32 MHz (VCO2 = 5898.24 MHz) from APLL2.
HSDS output , VOD ≥ 800 mV from OUT4, OUT5, OUT6 and OUT7 or OUT2 and OUT3. 156.25 MHz from APLL3 output in all other output banks.		 110 150 fs
XO = 48 MHz,  fout = 161.1328125 MHz or 322.265625 MHz (VCO2 = 5800.78125 MHz), or 212.5 MHz (VCO2 = 5950 MHz) from APLL2. 
HSDS output , VOD ≥ 800 mV from  OUT4, OUT5, OUT6 and OUT7. 156.25 MHz from APLL3 output in all other output banks.		 110 150 fs
XO = 48 MHz,  fout = 156.25 MHz or 125 MHz (VCO2 = 5625 MHz), or 100 MHz (VCO2 = 5600 MHz) from APLL2.  HSDS output , VOD ≥ 800 mV from  OUT4, OUT5, OUT6 and OUT7 or OUT2 and OUT3. 156.25 MHz from APLL3 output in all other output banks. 110 150 fs
RJAPLL1 12 kHz to 20 MHz integrated RMS jitter for APLL1 outputs XO = 48 MHz, fout ≥ 100 MHz, HSDS output buffer VOD ≥ 800 mV 200 300 fs
PSNRVDDO_0_1 Power supply noise rejection VDD_0_1 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -105 dBc
PSNRVDDO_2_3 Power supply noise rejection VDD_2_3 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -105 dBc
PSNRVDDO_4_7 Power supply noise rejection VDDO_4_7 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -110 dBc
PSNRVDDO_8_13 Power supply noise rejection VDDO_8_13 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -110 dBc
PSNRVDD_APLL1_XO Power supply noise rejection VDD_APLL1_XO Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -100 dBc
PSNRVDD_APLL2 Power supply noise rejection VDD_APLL2 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -105 dBc
PSNRVDD_APLL3 Power supply noise rejection VDD_APLL3 Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -105 dBc
PSNRVDD_DIG Power supply noise rejection VDD_DIG Vcc = 3.3V, VN = 50 mVpp, HSDS, LVDS or LVPECL outputs. (12) -120 dBc
PCIe Jitter Characteristics
JPCIE-Gen1-CC PCIe Gen 1 (2.5 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 0.8 5 ps p-p
JPCIE-Gen2-CC PCIe Gen 2 (5.0 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 85 250 fs RMS
JPCIe-Gen3-CC PCIe Gen 3 (8 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 25 100 fs RMS
JPCIe-Gen4-CC PCIe Gen 4 (16 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 25 100 fs RMS
JPCIe-Gen5-CC PCIe Gen 5 (64 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 9 50 fs RMS
JPCIe-Gen6-CC PCIe Gen 6 (32 GT/s) Common Clock jitter APLL3, APLL2 or APLL1 output, 3x noise folding 6 40 fs RMS
DPLL Characteristics
fTDC TDC rate range for DPLL1/DPLL2/DPLL3 1E–6 26 MHz
dφ/dt Phase slew during switchover Programmable range 695 ns/s
DPLL-BW DPLL loop bandwidth Programmable loop bandwidth(16) 1E–3 4000 Hz
JPK DPLL closed-loop jitter peaking 0.1 dB
JTOL Jitter tolerance Compliant with G.8262 Options 1 and 2. Jitter modulation = 10 Hz, 25.78152 Gbps line rate 6455 UI p-p
DCO Characteristics
fDCO-DPLL DPLL DCO frequency tuning range DPLL3, DPLL2, DPLL1 -200 200 ppm
fDCO-APLL DCO frequency tuning range APLL3 in holdover or APLL only operation. -200 200 ppm
APLL2, APLL1 in holdover or APLL only operation. -1000 1000 ppm
Zero-Delay Mode (ZDM) Characteristics
fOUT-ZDM Output frequency range with ZDM enabled DPLL3: OUT0 or OUT10 1E–6 1250 MHz
DPLL2: OUT0 or OUT4 1E–6 700 MHz
DPLL1: OUT0 1E–6 1250 MHz
tDLY-ZDM Input-to-output propagation delay with ZDM enabled OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX, DPLLx_PH_OFFSET = 172500 150 ps
tDLY-VAR-ZDM Input-to-output propagation delay variation with ZDM enabled OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX, DPLLx_PH_OFFSET = 0 65 ±ps
1-PPS Reference Characteristics
tDPLL_FL DPLL frequency lock time with 1-PPS reference XO = 48 MHz, initial error = ±25 ppb, -180° ≤ Θ ≤ 180°. DPLL LBW = 10 mHz, frequency lock Δfout ≤ ±4.6 ppm 5 6 s
tDPLL_PL DPLL phase lock time with 1-PPS reference XO = 48 MHz, initial error = ±25 ppb, -180° ≤ Θ ≤ 180°. DPLL LBW = 10 mHz,  DPLL LBW = 10 mHz, phase lock ≤ ±100 ns 34 38 s
Hitless Switching Characteristics
tHIT Phase transient during switchover INx = 1 Hz, INy = 1 Hz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 10 mHz. 4 ± ps
INx = 8 kHz, INy = 8 kHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1 Hz 19 ± ps
Nx = 25 MHz, INy = 25 MHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1 Hz 1.8 ± ps
fHIT Frequency transient during switchover INx = 1 Hz,  INy = 1 Hz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 10 mHz 0.85 ± ppb
INx = 8 kHz, INy = 8 kHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1 Hz 0.45 ± ppb
INx = 25 MHz,  INy = 25 MHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1 Hz 0.63 ± ppb
Programmable Output Delay Characteristics
tANA-DLY Analog delay step size (13) APLL3 = 2457.6 MHz, VCO post-divider = 2, 0.5x range scale, 1 Hz ≤ OUTx  ≤ 122.88 MHz, ANA_DELAY_LINEARITY_CODE = 2 13.13 ps
APLL3 = 2457.6 MHz, VCO post-divider= 1, 2x range scale, 1 Hz ≤ OUTx  ≤ 122.88 MHz, ANA_DELAY_LINEARITY_CODE = 5 26.25 ps
APLL2 = 5625.0 MHz, VCO post-divider = 3, 1x range scale, 1 Hz ≤ OUTx  ≤ 156.25 MHz, ANA_DELAY_LINEARITY_CODE = 3 17.2 ps
APLL2= 5625.0 MHz, VCO post-divider = 4; 1x range scale, 1 Hz ≤ OUTx  ≤ 156.25 MHz, ANA_DELAY_LINEARITY_CODE = 4 22.9 ps
tANA-DLY-ERR Analog delay step size error APLL3 = 2457.6 MHz, VCO post-divider = 2, 0.5x range scale, 1 Hz ≤ OUTx  ≤ 122.88 MHz, ANA_DELAY_LINEARITY_CODE = 2 -6.56 6.56 ps
APLL3 = 2457.6 MHz, VCO post-divider= 1, 2x range scale, 1 Hz ≤ OUTx  ≤ 122.88 MHz, ANA_DELAY_LINEARITY_CODE = 5 -13.13 13.13 ps
APLL2 = 5625.0 MHz, VCO post-divider = 3, 1x range scale, 1 Hz ≤ OUTx  ≤ 156.25 MHz, ANA_DELAY_LINEARITY_CODE = 3 -8.6 8.6 ps
APLL2 = 5625.0 MHz, VCO post-divider = 4; 1x range scale, 1 Hz ≤ OUTx  ≤ 156.25 MHz, ANA_DELAY_LINEARITY_CODE = 4 -11.45 11.45 ps
tANA-DLY-RANGE Analog delay range 31 × tANA-DLY ps
tANA-DLY-ACC Analog delay accuracy Analog delay absolute accuracy for any setting N = 0 to 31 across analog delay range. Worst case error of actual value relative to expected value N × tANA-DLY-STEP for ANA_DELAY_LINEARITY_CODE = 3, 4, 5 -25 25 ps
tANA-DLY-LIN Analog delay linearity (14) ANA_DELAY_LINEARITY_CODE = 2 333 450 ps
ANA_DELAY_LINEARITY_CODE = 3 450 600 ps
ANA_DELAY_LINEARITY_CODE = 4 600 750 ps
ANA_DELAY_LINEARITY_CODE = 5 750 1050 ps
tDIG-DLY Digital delay step size VCO post-divider frequency output = 2457.6 MHz ,  half step setting 196.6 ps
VCO post-divider frequency output = 2457.6 MHz, full step setting 786.4 ps
3-Level Logic Input Characteristics (GPIO0, GPIO1, GPIO2, SCS_ADD)
VIH Input high voltage 1.4 V
VIM Input mid voltage 0.6 0.95 V
VIM Input mid voltage self-bias Input floating with internal bias and PD# pulled low 0.7 0.9 V
RIM-PD Internal pulldown resistor for mid level self-bias (15) 145 163 180 kΩ
RIM-PU Internal pullup for mid level self-bias (15) 470 526 580 kΩ
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD –40 40 µA
IIL Input low current VIL = GND –40 40 µA
CIN Input capacitance 2 pF
2-Level Logic Input Characteristics (PD#, SCK, SDIO, SCS_ADD; GPIO0, GPIO1 and GPIO2 after power up)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD, except PD# –40 40 µA
IIL Input low current VIL = GND, except PD# –40 40 µA
IIH Input high current VIH = VDD, PD# with internal 200 kΩ pull-up –57 24 µA
IIL Input low current VIL = GND, PD# with internal 200 kΩ pull-up –57 24 µA
tWIDTH Input pulse width for GPIO SYNC, SYSREF request, TEC trigger, DPLL input selection, FDEV trigger and FDEV_dir Monotonic edges 200 ns
CIN Input capacitance 2 pF
Logic Output Characteristics (GPIO0, GPIO1, GPIO2, SDIO)
VOH Output high voltage IOH = 1 mA 2.4 V
VOL Output low voltage IOL = 1 mA 0.4 V
tR/tF Output rise/fall time 20% to 80%, LVCMOS mode, 1 kΩ to GND 500 ps
Open Drain Output (GPIO0, GPIO1, GPIO2, SDA)
VOL Output Low Level IOL = 3 mA 0.3 V
IOL = 6 mA 0.6 V
IOH Output Leakage Current -15 15 µA
SPI Timing Requirements (SDIO, SCK, SCS_ADD)
fSCK SPI clock rate 20 MHz
SPI clock rate; during SRAM read and write operations 5 10 MHz
t1 SCS to SCK setup time (start communication cycle) 10 ns
t2 SDI to SCK setup time 10 ns
t3 SDI to SCK hold time 10 ns
t4 SCK high time 25 ns
t5 SCK low time 25 ns
t6 SCK to SDO valid read-back data 20 ns
t7 SCS pulse width 20 ns
t8 SCK to SCS setup time (end communication cycle) 10 ns
I2C Timing Requirements (SDA, SCL)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.5 V
IIH Input leakage –15 15 µA
CIN Input capacitance 2 pF
VOL Output low voltage IOL = 3 mA 0.3 V
VOL Output low voltage IOL = 6 mA 0.6 V
fSCL I2C clock rate Standard 100 kHz
Fast mode 400
tSU(START) START condition setup time SCL high before SDA low 0.6 µs
tH(START) START condition hold time SCL low after SDA low 0.6 µs
tW(SCLH) SCL pulse width high 0.6 µs
tW(SCLL) SCL pulse width low 1.3 µs
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 µs
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS ≤ 400 pF 300 ns
tSU(STOP) STOP condition setup time 0.6 µs
tBUS Bus free time between STOP and START 1.3 µs
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
EEPROM Characteristics
nEE-CYC EEPROM programming cycles 100 cycle
tSRAM-R/W EEPROM SRAM read/write time delay between bytes 0 ms
(1) This is the current consumption of one XO doubler. Each of the three XO doublers consume the same current.
(2) This is the current consumption of one DPLL. Each of the three DPLLs consume the same current.
(3) REFx_ITYPE = 8 or 12.
(4) REFx_ITYPE = 1, 3 or 5, non-driven input directly tied to GND, capacitor to GND or 50-Ω to GND.
(5) REFx_ITYPE = 1, 3 or 5.
(6) Combination of common mode voltage and DC coupled different input voltage must not exceed Absolute Maximum Ratings.
(7) When XO input frequency is greater than the APLL phase detector maximum supported comparison frequency, the APLL R divider must be set to minimum of divide by 2.
(8) Register XO_ITYPE = 8 or 12.
(9) Register XO_ITYPE = 1, 3 or 5
(10) APLL3 post divider bypassed by setting P1APLL3  = 1. OUT0 to OUT13 sourced from channel dividers.
(11) PSNR is the single-sideband spur level measured in dBc when sinusoidal noise with amplitude VN and frequency between 100 kHz and 10 MHz is injected onto VDD and VDDO pins with 1.0 µF decoupling capacitance. 
(12) Output dividers are synchronized. SYNC status achieved from power up or SYNC_SW.
(13) Typical analog delay step size based on APLL post-divider output period divided by 31, times the analog delay range scale value 0.5, 1 or 2.
(14) Analog delay linearity typically selected based on the period of the analog delay range, tANA-DLY-RANGE.
(15) Variation of internal pullup resistor will track variation of pulldown resistor to maintain a consistent med voltage self-bias ratio.
(16) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.