SNAS676D October 2015 – October 2017 LMK61A2-100M , LMK61A2-125M , LMK61A2-156M , LMK61A2-312M , LMK61A2-644M , LMK61E0-050M , LMK61E0-155M , LMK61E0-156M , LMK61E2-100M , LMK61E2-125M , LMK61E2-156M , LMK61E2-312M , LMK61I2-100M
PRODUCTION DATA.
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The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
Changes from C Revision (September 2017) to D Revision
Changes from B Revision (March 2017) to C Revision
Changes from A Revision (November 2015) to B Revision
Changes from * Revision (October 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
POWER | |||
GND | 3 | Ground | Device Ground. |
VDD | 6 | Analog | 3.3 V Power Supply. |
OUTPUT BLOCK | |||
OUTP, OUTN | 4, 5 | Universal | Differential Output Pair (LVPECL, LVDS or HCSL). |
DIGITAL CONTROL / INTERFACES | |||
NC | 2 | N/A | No Connect. |
OE | 1 | LVCMOS | Output Enable (internal pullup). When set to low, output pair is disabled and set at high impedance. |