SNAS676D October   2015  – October 2017 LMK61A2-100M , LMK61A2-125M , LMK61A2-156M , LMK61A2-312M , LMK61A2-644M , LMK61E0-050M , LMK61E0-155M , LMK61E0-156M , LMK61E2-100M , LMK61E2-125M , LMK61E2-156M , LMK61E2-312M , LMK61I2-100M

PRODUCTION DATA.  

1. 1 Features
2. 2 Applications
3. 3 Description
4. 4 Revision History
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics - Power Supply
   6. 6.6  LVPECL Output Characteristics
   7. 6.7  LVDS Output Characteristics
   8. 6.8  HCSL Output Characteristics
   9. 6.9  OE Input Characteristics
   10. 6.10 Frequency Tolerance Characteristics
   11. 6.11 Power-On/Reset Characteristics (VDD)
   12. 6.12 PSRR Characteristics
   13. 6.13 PLL Clock Output Jitter Characteristics
   14. 6.14 Typical 156.25-MHz Output Phase Noise Characteristics
   15. 6.15 Additional Reliability and Qualification
   16. 6.16 Typical Characteristics
7. 7 Parameter Measurement Information
   1. 7.1 Device Output Configurations
8. 8 Power Supply Recommendations
9. 9 Layout
   1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
10. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
11. 11Mechanical, Packaging, and Orderable Information