JAJSLN7E
April 2022 – January 2024
LMK6C
,
LMK6D
,
LMK6H
,
LMK6P
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Ordering Information
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Environmental Compliance
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Thermal Information
6.7
Electrical Characteristics
6.8
Timing Diagrams
6.9
Typical Characteristics
7
Parameter Measurement Information
7.1
Device Output Configurations
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Bulk Acoustic Wave (BAW)
8.3.2
Device Block-Level Description
8.3.3
Function Pin(s)
8.3.4
Clock Output Interfacing and Termination
8.3.5
Temperature Stability
8.3.6
Mechanical Robustness
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Ensuring Thermal Reliability
9.4.1.2
Recommended Solder Reflow Profile
9.4.2
Layout
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DLE|4
MPQF589A
DLF|4
MPQF590C
サーマルパッド・メカニカル・データ
DLE|4
QFND773A
DLF|4
QFND771A
発注情報
jajsln7e_oa
jajsln7e_pm
6.9
Typical Characteristics
Figure 6-3
Current Consumption vs Frequency
(LVCMOS, 1.8 V)
Figure 6-5
Current Consumption vs Frequency
(LVCMOS, 3.3 V)
Figure 6-7
Current Consumption vs Frequency
(HCSL, 2.5 V)
Figure 6-9
Current Consumption vs Frequency
(LVPECL, 1.8 V)
Figure 6-11
Current Consumption vs Frequency
(LVPECL, 3.3 V)
Figure 6-13
Current Consumption vs Frequency
(LVDS, 2.5 V)
Figure 6-15
RMS Jitter vs Frequency (100 MHz to 200 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C
Figure 6-17
RMS Jitter vs Frequency (200 MHz to 300 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C
Figure 6-19
RMS Jitter vs Frequency (300 MHz to 400 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C
Figure 6-21
RMS Jitter vs Frequency (Below 100 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C
Figure 6-23
RMS Jitter vs Frequency ( 100 MHz - 200 MHz) for LVCMOS; TYPICAL 3.3 V, 25°C
Figure 6-25
Duty Cycle (%) vs Frequency vs Power Supply; 25°C
Figure 6-27
Duty Cycle (%) vs Frequency Over Temperature Range for LVCMOS; 3.3 V
Figure 6-4
Current Consumption vs Frequency
(LVCMOS, 2.5 V)
Figure 6-6
Current Consumption vs Frequency
(HCSL, 1.8 V)
Figure 6-8
Current Consumption vs Frequency
(HCSL, 3.3 V)
Figure 6-10
Current Consumption vs Frequency
(LVPECL, 2.5 V)
Figure 6-12
Current Consumption vs Frequency
(LVDS, 1.8 V)
Figure 6-14
Current Consumption vs Frequency
(LVDS, 3.3 V)
Figure 6-16
RMS Jitter vs Frequency (100 MHz to 200 MHz) for LVDS; TYPICAL 3.3 V, 25°C
Figure 6-18
RMS Jitter vs Frequency (200 MHz to 300 MHz) for LVDS; TYPICAL 3.3 V, 25°C
Figure 6-20
RMS Jitter vs Frequency (300 MHz to 400 MHz) for LVDS; TYPICAL 3.3 V, 25°C
Figure 6-22
RMS Jitter vs Frequency (Below 100 MHz) for LVDS; TYPICAL 3.3 V, 25°C
Figure 6-24
RMS Jitter vs Frequency ( 10 MHz - 100 MHz) for LVCMOS; TYPICAL 3.3 V, 25°C
Figure 6-26
Duty Cycle (%) vs Temperature vs Power Supply; 50-MHz Frequency