7.3.1 Potentiostat Circuitry

The core of the LMP91002 is a potentiostat circuit. It consists of a differential input amplifier used to compare the potential between the working and reference electrodes to a zero bias potential.. The error signal is amplified and applied to the counter electrode (through the Control Amplifier - A1). Any changes in the impedance between the working and reference electrodes will cause a change in the voltage applied to the counter electrode, in order to maintain the constant voltage between working and reference electrodes. A Transimpedance Amplifier connected to the working electrode, is used to provide an output voltage that is proportional to the cell current. The working electrode is held at virtual ground (Internal ground) by the transimpedance amplifier. The potentiostat will compare the reference voltage to the desired bias potential and adjust the voltage at the counter electrode to maintain the proper working-to-reference voltage.

7.3.2 Transimpedance Amplifier

The transimpedance amplifier (TIA in Functional Block Diagram) has 7 programmable internal gain resistors. This accommodates the full scale ranges of most existing sensors. Moreover an external gain resistor can be connected to the LMP91002 between C1 and C2 pins. The gain is set through the I²C interface.

7.3.3 Control Amplifier

The control amplifier (A1 op amp in Functional Block Diagram) provides initial charge to the sensor. A1 has the capability to drive up to 10mA into the sensor in order to to provide a fast initial conditioning. A1 is able to sink and source current according to the connected gas sensor (reducing or oxidizing gas sensor). It can be powered down to reduce system power consumption. However powering down A1 is not recommended, as it may take a long time for the sensor to recover from this situation.

7.3.4 Internal Zero

The internal Zero is the voltage at the non-inverting pin of the TIA. The internal zero can be programmed to be either 67%, 50% or 20%, of the supply, or the external reference voltage. This provides both sufficient headroom for the counter electrode of the sensor to swing, in case of sudden changes in the gas concentration, and best use of the ADC’s full scale input range.

The Internal zero is provided through an internal voltage divider (Vref divider box in Functional Block Diagram). The divider is programmed through the I²C interface.

7.3.5 2-Lead Galvanic Cell in Potentiostat Configuration

When the LMP91002 is interfaced to a galvanic cell (for instance to an Oxygen gas sensor) referred to a reference, the Counter and the Reference pin of the LMP91002 are shorted together and connected to negative electrode of the galvanic cell. The positive electrode of the galvanic cell is then connected to the Working pin of the LMP91002.

The LMP91002 is then configured in 3-lead amperometric cell mode (as for amperometric cell). In this configuration the Control Amplifier (A1) is ON and provides the internal zero voltage. The transimpedance amplifier (TIA) is also ON, it converts the current generated by the gas sensor in a voltage, according to the transimpedance gain:

Gain= R_TIA

If different gains are required, an external resistor can be connected between the pins C1 and C2. In this case the internal feedback resistor should be programmed to “external”.

Figure 12. Two-Lead Sensor Connections

7.4.1 Timeout Feature

The timeout is a safety feature to avoid bus lockup situation. If SCL is stuck low for a time exceeding t_timeout, the LMP91002 will automatically reset its I²C interface. Also, in the case the LMP91002 hangs the SDA for a time exceeding t_timeout, the LMP91002’s I²C interface will be reset so that the SDA line will be released. Since the SDA is an open-drain with an external resistor pull-up, this also avoids high power consumption when LMP91002 is driving the bus and the SCL is stopped.

7.5.1 I²C Interface

The I²C compatible interface operates in Standard mode (100kHz). Pull-up resistors or current sources are required on the SCL and SDA pins to pull them high when they are not being driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The LMP91002 comes with a 7 bit bus fixed address: 1001 000.

7.5.2 Write and Read Operation

In order to start any read or write operation with the LMP91002, MENB needs to be set low during the whole communication. Then the master generates a start condition by driving SDA from high to low while SCL is high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have been transmitted by the master, SDA is released by the master and the LMP91002 either ACKs or NACKs the address. If the slave address matches, the LMP91002 ACKs the master. If the address doesn't match, the LMP91002 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register address pointer. Then the LMP91002 ACKs the transfer by driving SDA low. Next, the master sends the 8-bit data to the LMP91002. Then the LMP91002 ACKs the transfer by driving SDA low. At this point the master should generate a stop condition and optionally set the MENB at logic high level (refer to Figure 15).

A read operation requires the LMP91002 address pointer to be set first, also in this case the master needs setting at low logic level the MENB, then the master needs to write to the device and set the address pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit, the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 15). Following this sequence, the LMP91002 sends out the 8-bit data of the register.

When just one LMP91002 is present on the I²C bus the MENB can be tied to ground (low logic level).

Figure 13. (a) Register Write Transaction

Figure 14. (b) Pointer Set Transaction

(c) Register read transaction

Figure 15. READ and WRITE Transaction

7.5.3 Connection of More Than One LMP91002 to the I²C Bus

The LMP91002 comes out with a unique and fixed I²C slave address. It is still possible to connect more than one LMP91002 to an I²C bus and select each device using the MENB pin. The MENB simply enables/disables the I²C communication of the LMP91002. When the MENB is at logic level low all the I²C communication is enabled, it is disabled when MENB is at high logic level.

In a system based on a μcontroller and more than one LMP91002 connected to the I²C bus, the I²C lines (SDA and SCL) are shared, while the MENB of each LMP91002 is connected to a dedicate GPIO port of the μcontroller.

The μcontroller starts communication asserting one out of N MENB signals where N is the total number of LMP91002s connected to the I²C bus. Only the enabled device will acknowledge the I²C commands. After finishing communicating with this particular LMP91002, the microcontroller de-asserts the corresponding MENB and repeats the procedure for other LMP91002s. Figure 16 shows the typical connection when more than one LMP91002 is connected to the I²C bus.

Figure 16. More than one LMP91002 on I²C bus

Table 1. Register Map

7.6.1 STATUS Register (Offset = 00h)

Status Register. The status bit is an indication of the LMP91002's power-on status. If its readback is “0”, the LMP91002 is not ready to accept other I²C commands.

7.6.2 LOCK Register (Offset = 01h)

Protection Register. The lock bit enables and disables the writing of the TIACN and the REFCN registers. To change the content of the TIACN and the REFCN registers, the lock bit must be set to “0”.

7.6.3 TIACN Register (Offset = 10h)

TIA Control Register. The parameters in the TIA control register allow the configuration of the transimpedance gain (R_TIA).

7.6.4 REFCN Register (Offset = 11h)

Reference Control Register. The parameters in the Reference control register allow the configuration of the Internal zero, and reference source. When the reference source is external, the reference is provided by a reference voltage connected to the VREF pin. In this condition the internal zero is defined as a percentage of VREF voltage instead of the supply voltage.

7.6.5 MODECN Register (Offset = 12h)

Mode Control Register. The parameters in the mode register allow the configuration of the operation mode of the LMP91002.