SNIS163B April   2012  – October 2015 LMP91002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface
    7. 6.7 Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Potentiostat Circuitry
      2. 7.3.2 Transimpedance Amplifier
      3. 7.3.3 Control Amplifier
      4. 7.3.4 Internal Zero
      5. 7.3.5 2-Lead Galvanic Cell in Potentiostat Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 Timeout Feature
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 Write and Read Operation
      3. 7.5.3 Connection of More Than One LMP91002 to the I2C Bus
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Register (Offset = 00h)
      2. 7.6.2 LOCK Register (Offset = 01h)
      3. 7.6.3 TIACN Register (Offset = 10h)
      4. 7.6.4 REFCN Register (Offset = 11h)
      5. 7.6.5 MODECN Register (Offset = 12h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gas Sensor Interface
        1. 8.1.1.1 3-Lead Amperometric Cell In Potentiostat Configuration
      2. 8.1.2 Sensor Test Procedure
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Smart Gas Sensor Analog Front End
        2. 8.2.2.2 Smart Gas Sensor AFES on I2C Bus
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Consumption
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)(3)
MIN MAX UNIT
Voltage between any two pins 6 V
Current through VDD or VSS 50 mA
Current sunk and sourced by CE pin 10 mA
Current out of other pins(2) 5 mA
Junction temperature(2) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see SNOA549.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine Model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.3 Recommended Operating Conditions

MIN MAX UNIT
Supply voltage VS = (VDD - AGND) 2.7 3.6 V
Temperature(1) –40 85 °C
(1) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC(1) LMP91002 UNIT
NHL (WSON)
14 PINS
RθJA Junction-to-ambient thermal resistance (2) 44 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.

6.5 Electrical Characteristics

Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF = 2.5 V, Internal Zero = 20% VREF.(1)
PARAMETER TEST CONDITIONS MIN(4) TYP(2) MAX(4) UNIT
POWER SUPPLY SPECIFICATION
IS Supply current 3-lead amperometric cell mode
MODECN = 0x03		 TA = 25ºC 10 13.5 µA
At the temperature extremes 15
Standby mode
MODECN = 0x02		 TA = 25ºC 6.5 8
At the temperature extremes 10
Deep sleep mode
MODECN = 0x00		 TA = 25ºC 0.6 0.85
At the temperature extremes 1
POTENTIOSTAT
IRE Input bias current at RE pin VDD = 2.7 V;
Internal zero 50% VDD		 TA = 25ºC –90 90 pA
At the temperature extremes –800 800
VDD = 3.6 V;
Internal zero 50% VDD		 TA = 25ºC –90 90
At the temperature extremes –900 900
ICE Minimum operating current capability Sink 750 µA
Source 750
Minimum charging capability(5) Sink 10 mA
Source 10
AOL_A1 Open-loop voltage gain of control loop operational amplifier (A1) 300 mV ≤ VCE ≤
Vs – 300 mV, –750 µA ≤ ICE ≤ 750 µA		 TA = 25ºC 120 dB
At the temperature extremes 104
en_RW Low frequency integrated noise between RE pin and WE pin 0.1 Hz to 10 Hz(6) 3.4 µVpp
VOS_RW WE voltage offset referred to RE 0% VREF, internal zero = 20% VREF,
at the temperature extremes		 –550 550 µV
0% VREF, internal zero = 50% VREF,
at the temperature extremes		 –550 550
0% VREF, internal zero = 67% VREF,
at the temperature extremes		 –550 550
TcVOS_RW WE voltage offset drift referred to RE from –40°C to 85°C(3) 0% VREF, internal zero = 20% VREF –4 4 µV/°C
0% VREF, internal zero = 50% VREF –4 4
0% VREF, internal zero = 67% VREF –4 4
TIA_GAIN Transimpedance gain accuracy 5%
Linearity ±0.05%
Programmable TIA gains 7 programmable gain resistors 2.75
3.5
7
14
35
120
350		 kΩ
Maximum external gain resistor 350
TIA_ZV Internal zero voltage 3 programmable percentages of VREF 20%
50%
67%
3 programmable percentages of VDD 20%
50%
67%
Internal zero voltage accuracy ±0.04%
RL Load resistor 10 Ω
Load accuracy 5%
PSRR Power supply rejection ratio at RE pin 2.7 V ≤ VDD ≤ 5.25 V Internal zero 20% VREF 80 110 dB
Internal zero 50% VREF 80 110
Internal zero 67% VREF 80 110
EXTERNAL REFERENCE SPECIFICATION(3)
VREF External voltage reference range 1.5 VDD V
Input impedance 10 MΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(3) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.Starting from the measured voltage offset at temperature T1 (VOS_RW(T1)), the voltage offset at temperature T2 (VOS_RW(T2)) is calculated according the following formula: VOS_RW(T2)=VOS_RW(T1)+ABS(T2–T1)* TcVOS_RW.
(4) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(5) At such currents no accuracy of the output voltage can be expected.
(6) This parameter includes both A1 and TIA's noise contribution.

6.6 I2C Interface

Unless otherwise specified, all limits ensured for at TA = 25°C, VS= (VDD – AGND), 2.7 V <VS< 3.6 V and AGND = DGND = 0 V, VREF = 2.5 V.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(4) MAX(2) UNIT
VIH Input High Voltage At the temperature extremes 0.7*VDD V
VIL Input Low Voltage At the temperature extremes 0.3*VDD V
VOL Output Low Voltage IOUT = 3 mA, at the temperature extremes 0.4 V
Hysteresis(3) At the temperature extremes 0.1*VDD V
CIN Input Capacitance on all digital pins At the temperature extremes 0.5 pF
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) This parameter is specified by design or characterization.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.

6.7 Timing Characteristics

Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF = 2.5 V, Internal Zero= 20% VREF. All limits apply at the temperature extremes. Refer to timing diagram in Figure 1(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL Clock Frequency At the temperature extremes 10 100 kHz
tLOW Clock Low Time At the temperature extremes 4.7 µs
tHIGH Clock High Time At the temperature extremes 4 µs
tHD;STA Data valid After this period, the first clock pulse is generated at the temperature extremes 4 µs
tSU;STA Set-up time for a repeated START condition At the temperature extremes 4.7 µs
tHD;DAT Data hold time(4)
At the temperature extremes 0 ns
tSU;DAT Data Set-up time At the temperature extremes 250 ns
tf SDA fall time(5) IL ≤ 3 mA, CL ≤ 400 pF,
at the temperature extremes		 250 ns
tSU;STO Set-up time for STOP condition At the temperature extremes 4 µs
tBUF Bus free time between a STOP and START condition At the temperature extremes 4.7 µs
tVD;DAT Data valid time At the temperature extremes 3.45 µs
tVD;ACK Data valid acknowledge time At the temperature extremes 3.45 µs
tSP Pulse width of spikes that must be suppressed by the input filter(5) At the temperature extremes 50 ns
t_timeout SCL and SDA Timeout At the temperature extremes 25 100 ms
tEN;START I2C Interface Enabling At the temperature extremes 600 ns
tEN;STOP I2C Interface Disabling At the temperature extremes 600 ns
tEN;HIGH time between consecutive I2C interface enabling and disabling At the temperature extremes 600 ns
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if current is forced into pin.
(3) In case of external reference connected, the noise of the reference has to be added.
(4) LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
(5) This parameter is specified by design or characterization.
LMP91002 30182541.gif Figure 1. I2C Interface Timing Diagram

6.8 Typical Characteristics

Unless otherwise specified, TA = 25°C, VS= (VDD – AGND), 2.7 V <VS< 3.6 V and AGND = DGND = 0 V, VREF = 2.5 V.
LMP91002 30182563.gif Figure 2. Input VOS_RW vs Temperature
LMP91002 30182560.gif Figure 4. AC PSRR vs Frequency
LMP91002 30182597.gif Figure 6. Supply Current vs VDD (Deep Sleep Mode)
LMP91002 30182592.gif Figure 8. Supply Current vs VDD (Standby Mode)
LMP91002 30182593.gif Figure 10. Supply Current vs VDD (3-Lead Amperometric Mode)
LMP91002 30182562.gif Figure 3. Input VOS_RW vs VDD
LMP91002 30182591.gif Figure 5. Supply Current vs Temperature (Deep Sleep Mode)
LMP91002 30182587.gif Figure 7. Supply Current vs Temperature (Standby Mode)
LMP91002 30182586.gif Figure 9. Supply Current vs Temperature (3-Lead Amperometric Mode)
LMP91002 30182598.gif Figure 11. 0.1-Hz to 10-Hz Noise