JAJSHJ7D October   2011  – June 2019 LMR10515

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Description: 5-Pin SOT-23
    2.     Pin Descriptions 6-Pin WSON
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Ratings
    3. 7.3 Electrical Characteristics
    4. 7.4 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft-Start
      2. 8.3.2 Output Overvoltage Protection
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Current Limit
      5. 8.3.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1 Custom Design With WEBENCH® Tools
        2. 9.2.1.2 Inductor Selection
        3. 9.2.1.3 Input Capacitor
        4. 9.2.1.4 Output Capacitor
        5. 9.2.1.5 Catch Diode
        6. 9.2.1.6 Output Voltage
        7. 9.2.1.7 Calculating Efficiency, And Junction Temperature
      2. 9.2.2 Application Curves
      3. 9.2.3 Other System Examples
        1. 9.2.3.1 LMR10510x Design Example 1
        2. 9.2.3.2 Lmr10510X Design Example 2
        3. 9.2.3.3 LMR10510Y Design Example 3
        4. 9.2.3.4 LMR10510Y Design Example 4
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Definitions
    4. 10.4 WSON Package
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Overview

The following operating description of the LMR10515 refers to Functional Block Diagram and to the waveforms in Figure 14. The LMR10515 supplies a regulated output voltage by switching the internal PMOS control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal PMOS control switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL) increases with a linear slope. IL is measured by the current sense amplifier, which generates an output proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch diode, which forces the SW pin to swing below ground by the forward voltage (VD) of the Schottky catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage.

LMR10515 30166166.gifFigure 14. Typical Waveforms