JAJSHL8B June   2012  – June 2019 LMR12015 , LMR12020

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Ratings
    3. 6.3 Electrical Characteristics
    4. 6.4 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Function
      2. 7.3.2  Low Input Voltage Considerations
      3. 7.3.3  High Output Voltage Considerations
      4. 7.3.4  Frequency Synchronization
      5. 7.3.5  Current Limit
      6. 7.3.6  Frequency Foldback
      7. 7.3.7  Soft Start
      8. 7.3.8  Output Overvoltage Protection
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Operation Modes
      1. 7.4.1 Enable Pin / Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1  Custom Design With WEBENCH® Tools
        2. 8.2.1.2  Inductor Selection
          1. 8.2.1.2.1 Inductor Calculation Example
          2. 8.2.1.2.2 Inductor Material Selection
        3. 8.2.1.3  Input Capacitor
        4. 8.2.1.4  Output Capacitor
        5. 8.2.1.5  Catch Diode
        6. 8.2.1.6  Boost Diode (Optional)
        7. 8.2.1.7  Boost Capacitor
        8. 8.2.1.8  Output Voltage
        9. 8.2.1.9  Feedforward Capacitor (Optional)
        10. 8.2.1.10 Calculating Efficiency and Junction Temperature
          1. 8.2.1.10.1 Schottky Diode Conduction Losses
          2. 8.2.1.10.2 Inductor Conduction Losses
          3. 8.2.1.10.3 MOSFET Conduction Losses
          4. 8.2.1.10.4 MOSFET Switching Losses
          5. 8.2.1.10.5 IC Quiescent Losses
          6. 8.2.1.10.6 MOSFET Driver Losses
          7. 8.2.1.10.7 Total Power Losses
          8. 8.2.1.10.8 Efficiency Calculation Example
          9. 8.2.1.10.9 Calculating the LMR2015/20 Junction Temperature
      2. 8.2.2 Application Curves
      3. 8.2.3 LMR12015/20 Circuit Examples
  9. 9 Layout
    1. 9.1 Layout Considerations
      1. 9.1.1 Compact Layout
      2. 9.1.2 Ground Plane and Shape Routing
      3. 9.1.3 FB Loop
      4. 9.1.4 PCB Summary
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 10.1.2 開発サポート
        1. 10.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 10.2 関連リンク
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3 Electrical Characteristics

Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating Temperature Range (TJ = -40°C to 125°C). VIN = 12V, and VBOOST - VSW = 4.3V unless otherwise specified. Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PARAMETERS
VFB Feedback Voltage TJ = 0°C to 85°C 0.990 1.0 1.010 V
TJ = -40°C to 125°C 0.984 1.0 1.014
ΔVFB/ΔVIN Feedback Voltage Line Regulation VIN = 3V to 20V 0.003 % / V
IFB Feedback Input Bias Current 20 100 nA
OVP Over Voltage Protection, VFB at which PWM Halts. 1.13 V
UVLO Undervoltage Lockout VIN Rising until VSW is Switching 2.60 2.75 2.90 V
UVLO Hysteresis VIN Falling from UVLO 0.30 0.47 0.6
SS Soft Start Time 0.5 1 1.5 ms
IQ Quiescent Current, IQ = IQ_AVIN + IQ_PVIN VFB = 1.1 (not switching) 2.4 mA
Quiescent Current, IQ = IQ_AVIN + IQ_PVIN VEN = 0V (shutdown) 70 nA
IBOOST Boost Pin Current fSW= 2 MHz 8.2 10 mA
fSW= 1 MHz 4.4 6
OSCILLATOR
fSW Switching Frequency SYNC = GND 1.75 2 2.3 MHz
VFB_FOLD FB Pin Voltage where SYNC input is overridden. 0.53 V
fFOLD_MIN Frequency Foldback Minimum VFB = 0V 220 250 kHz
LOGIC INPUTS (EN, SYNC)
fSYNC SYNC Frequency Range 1 2.35 MHz
VIL EN, SYNC Logic low threshold Logic Falling Edge 0.4 V
VIH EN, SYNC Logic high threshold Logic Rising Edge 1.8
tSYNC_HIGH SYNC, Time Required above VIH to Ensure a Logical High. 100 ns
tSYNC_LOW SYNC, Time Required below VIL to Ensure a Logical Low. 100 ns
ISYNC SYNC Pin Current VSYNC < 5V 20 nA
IEN Enable Pin Current VEN = 3V 6 15 µA
VIN = VEN = 20V 50 100
INTERNAL MOSFET
RDS(ON) Switch ON Resistance 150 320 mΩ
ICL Switch Current Limit LMR12020 2.5 4.0 A
LMR12015 2.0 3.7
DMAX Maximum Duty Cycle SYNC = GND 85 93%
tMIN Minimum on time 65 ns
ISW Switch Leakage Current 40 nA
BOOST LDO
VLDO Boost LDO Output Voltage 3.9 V
THERMAL
TSHDN Thermal Shutdown Temperature(3) Junction temperature rising 165 °C
Thermal Shutdown Hysteresis Junction temperature hysteresis 15 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions.
(2) Human body model, 1.5 kΩ in series with 100 pF.
(3) Thermal shutdown occurs if the junction temperature exceeds 165°C. The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/θJA .
(4) All numbers apply for packages soldered directly onto a 3” × 3” PC board with 2 oz. copper on 4 layers in still air.
(5) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.