JAJSHL8B June   2012  – June 2019 LMR12015 , LMR12020

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Descriptions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Ratings
    3. 6.3 Electrical Characteristics
    4. 6.4 Typical Performance Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Function
      2. 7.3.2  Low Input Voltage Considerations
      3. 7.3.3  High Output Voltage Considerations
      4. 7.3.4  Frequency Synchronization
      5. 7.3.5  Current Limit
      6. 7.3.6  Frequency Foldback
      7. 7.3.7  Soft Start
      8. 7.3.8  Output Overvoltage Protection
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Operation Modes
      1. 7.4.1 Enable Pin / Shutdown Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1  Custom Design With WEBENCH® Tools
        2. 8.2.1.2  Inductor Selection
          1. 8.2.1.2.1 Inductor Calculation Example
          2. 8.2.1.2.2 Inductor Material Selection
        3. 8.2.1.3  Input Capacitor
        4. 8.2.1.4  Output Capacitor
        5. 8.2.1.5  Catch Diode
        6. 8.2.1.6  Boost Diode (Optional)
        7. 8.2.1.7  Boost Capacitor
        8. 8.2.1.8  Output Voltage
        9. 8.2.1.9  Feedforward Capacitor (Optional)
        10. 8.2.1.10 Calculating Efficiency and Junction Temperature
          1. 8.2.1.10.1 Schottky Diode Conduction Losses
          2. 8.2.1.10.2 Inductor Conduction Losses
          3. 8.2.1.10.3 MOSFET Conduction Losses
          4. 8.2.1.10.4 MOSFET Switching Losses
          5. 8.2.1.10.5 IC Quiescent Losses
          6. 8.2.1.10.6 MOSFET Driver Losses
          7. 8.2.1.10.7 Total Power Losses
          8. 8.2.1.10.8 Efficiency Calculation Example
          9. 8.2.1.10.9 Calculating the LMR2015/20 Junction Temperature
      2. 8.2.2 Application Curves
      3. 8.2.3 LMR12015/20 Circuit Examples
  9. Layout
    1. 9.1 Layout Considerations
      1. 9.1.1 Compact Layout
      2. 9.1.2 Ground Plane and Shape Routing
      3. 9.1.3 FB Loop
      4. 9.1.4 PCB Summary
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 10.1.2 開発サポート
        1. 10.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 10.2 関連リンク
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Frequency Synchronization

The LMR12015/20 switching frequency can be synchronized to an external clock, between 1.00 and 2.35 MHz, applied at the SYNC pin. At the first rising edge applied to the SYNC pin, the internal oscillator is overridden and subsequent positive edges will initiate switching cycles. If the external SYNC signal is lost during operation, the LMR12015/20 reverts to its internal 2-MHz oscillator within 1.5 µs. To disable frequency synchronization and utilize the internal 2-MHz oscillator, connect the SYNC pin to GND.

The SYNC pin gives the designer the flexibility to optimize their design. A lower switching frequency can be chosen for higher efficiency. A higher switching frequency can be chosen to keep EMI out of sensitive ranges such as the AM radio band. Synchronization can also be used to eliminate beat frequencies generated by the interaction of multiple switching power converters. Synchronizing multiple switching power converters will result in cleaner power rails.

The selected switching frequency (fSYNC) and the minimum on-time (tMIN) limit the minimum duty cycle (DMIN) of the device.

Equation 6. DMIN= tMIN × fSYNC

Operation below DMIN is not reccomended. The LMR12015/20 skips pulses to keep the output voltage in regulation, and the current limit is not ensured. The switching is in phase but no longer at the same switching frequency as the SYNC signal.