SNVSAA6A February   2015  – March 2015 LMR14050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Peak Current Mode Control
      2. 8.3.2  Slope Compensation
      3. 8.3.3  Sleep-mode
      4. 8.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Adjustable Output Voltage
      6. 8.3.6  Enable and Adjustable Under-voltage Lockout
      7. 8.3.7  External Soft-start
      8. 8.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 8.3.9  Over Current and Short Circuit Protection
      10. 8.3.10 Overvoltage Protection
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Set-Point
        2. 9.2.2.2 Switching Frequency
        3. 9.2.2.3 Output Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Schottky Diode Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor Selection
        8. 9.2.2.8 Soft-start Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input Voltages VIN, EN to GND -0.3 44 V
BOOT to GND -0.3 49
SS to GND -0.3 5
FB to GND -0.3 7
RT/SYNC to GND -0.3 3.6
Output Voltages BOOT to SW 6.5 V
SW to GND -3 44
TJ Junction temperature -40 150 °C
Tstg Storage temperature -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

PARAMETER DEFINITION VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM)(1) 2 kV
Charged device model (CDM)(2) 0.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Buck Regulator VIN 4 40 V
VOUT 0.8 28
BOOT 45
SW -1 40
FB 0 5
Control EN 0 40 V
RT/SYNC 0 3.3
SS 0 3
Frequency Switching frequency range at RT mode 200 2500 kHz
Switching frequency range at SYNC mode 250 2300
Temperature Operating junction temperature, TJ -40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) DDA UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 42.5 °C/W
ψJT Junction-to-top characterization parameter 9.9
ψJB Junction-to-board characterization parameter 25.4
RθJC(top) Junction-to-case (top) thermal resistance 56.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.8
RθJB Junction-to-board thermal resistance 25.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VIN = 4.0 V to 40 V
PARAMETER TEST CONDITION MIN TYP MAX UNIT
POWER SUPPLY (VIN PIN)
VIN Operation input voltage 4 40 V
UVLO Under voltage lockout thresholds Rising threshold 3.5 3.7 3.9 V
Hysteresis 285 mV
ISHDN Shutdown supply current VEN = 0 V, TA = 25°C, 4.0 V ≤ VIN ≤ 40 V 1.0 3.0 μA
IQ Operating quiescent current (non- switching) VFB = 1.0 V, TA = 25°C 40 μA
ENABLE (EN PIN)
VEN_TH EN Threshold Voltage 1.05 1.20 1.38 V
IEN_PIN EN PIN current Enable threshold +50 mV -4.6 μA
Enable threshold -50 mV -1.0
IEN_HYS EN hysteresis current -3.6 μA
EXTERNAL SOFT-START
ISS SS pin current TA = 25°C 3 μA
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage TJ = 25°C 0.744 0.750 0.756 V
TJ = -40°C to 125°C 0.735 0.750 0.765 V
HIGH-SIDE MOSFET
RDS_ON On-resistance VIN = 12 V, BOOT to SW = 5.8 V 90 180 mΩ
High-side MOSFET CURRENT LIMIT
ILIMT Current limit VIN = 12 V, TA = 25°C, Open Loop 6.2 7.9 9.7 A
THERMAL PERFORMANCE
TSHDN Thermal shutdown threshold 170 °C
THYS Hysteresis 12

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
fSW Switching frequency RT = 49.9 kΩ, 1% accuracy 400 500 600 kHz
VSYNC_HI SYNC clock high level threshold 1.7 V
VSYNC_LO SYNC clock low level threshold 0.5
TSYNC_MIN Minimum SYNC input pulse width Measured at 500 kHz, VSYNC_HI > 3 V, VSYNC_LO < 0.3 V 30 ns
TLOCK_IN PLL lock in time Measured at 500 kHz 100 µs
TON_MIN Minimum controllable on time VIN = 12 V, BOOT to SW = 5.8 V, ILoad = 1 A 75 ns
DMAX Maximum duty cycle fSW = 200 kHz 97 %

7.7 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 300 kHz, L = 6.5 µH, COUT = 47 µF x 4, TA = 25°C
LMR14050 D002_SNVSA81.gif
VOUT = 5 V fSW = 500 kHz
Figure 1. Efficiency vs. Load Current
LMR14050 D009_SNVSA81.gif
VOUT = 3.3 V fSW = 1 MHz
Figure 3. Efficiency vs. Load Current
LMR14050 D004_SNVSA81.gif
VOUT = 5 V fSW = 500 kHz
Figure 5. Load Regulation
LMR14050 D011_SNVSA81.gif
VOUT = 5 V fSW = 500 kHz
Figure 7. Dropout Curve
LMR14050 D013_SNVSA81.gif
VOUT = 5 V fSW = 2.2 MHz
Figure 9. Dropout Curve
LMR14050 D006_SNVSA81.gif
Figure 11. Shut-down Current and Quiescent Current
LMR14050 D003_SNVSA81.gif
VOUT = 5 V fSW = 1 MHz
Figure 2. Efficiency vs. Load Current
LMR14050 D010_SNVSA81.gif
VOUT = 3.3 V fSW = 2.2 MHz
Figure 4. Efficiency vs. Load Current
LMR14050 D005_SNVSA81.gif
VOUT = 5 V fSW = 500 kHz
Figure 6. Frequency vs VFB
LMR14050 D012_SNVSA81.gif
VOUT = 5V fSW = 1 MHz
Figure 8. Dropout Curve
LMR14050 D014_SNVSA81.gif
VOUT = 3.3 V fSW = 2.2 MHz
Figure 10. Dropout Curve
LMR14050 D007_SNVSA81.gif
IOUT = 0 A
Figure 12. UVLO Threshold