JAJSCQ0B December   2016  – March 2018 LMR23625-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷との関係、VIN = 12V、PFMオプション
  4. 4 改訂履歴
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 8.3.2  Adjustable Output Voltage
      3. 8.3.3  EN/SYNC
      4. 8.3.4  VCC, UVLO
      5. 8.3.5  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      6. 8.3.6  Power Good (PGOOD)
      7. 8.3.7  Internal Compensation and CFF
      8. 8.3.8  Bootstrap Voltage (BOOT)
      9. 8.3.9  Overcurrent and Short-Circuit Protection
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light Load Operation (PFM Option)
      5. 8.4.5 Light Load Operation (FPWM Option)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Output Voltage Setpoint
        3. 9.2.2.3  Switching Frequency
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Feed-Forward Capacitor
        7. 9.2.2.7  Input Capacitor Selection
        8. 9.2.2.8  Bootstrap Capacitor Selection
        9. 9.2.2.9  VCC Capacitor Selection
        10. 9.2.2.10 Undervoltage Lockout Setpoint
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Considerations
      3. 11.1.3 Feedback Resistors
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.5 Output Capacitor Selection

Choose the output capacitor(s), COUT, with care since it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the ESR of the output capacitors:

Equation 13. LMR23625-Q1 eq11_snvsa81.gif

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 14. LMR23625-Q1 equation_11_snvsah2.gif

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator control loop usually needs four or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for four clock cycles to maintain the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease occurs, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 15. LMR23625-Q1 equation_12_snvsah2.gif
Equation 16. LMR23625-Q1 equation17.gif

where

  • KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
  • IOL = Low level output current during load transient
  • IOH = High level output current during load transient
  • VUS = Target output voltage undershoot
  • VOS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV and chose KIND = 0.4. Equation 13 yields ESR no larger than 50 mΩ and Equation 14 yields COUT no smaller than 1.2 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 17.5 μF and 5.3 μF by Equation 15 and Equation 16 respectively. Consider of derating, one 33-μF, 16-V ceramic capacitor with 5-mΩ ESR is used.