Choose the output capacitor(s), C_OUT, with care because it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load-current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the equivalent series resistance (ESR) of the output capacitors:

Equation 14.

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 15.

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for four clock cycles to maintain the output voltage within the specified range. Equation 17 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 14 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 16.

Equation 17.

where

• I_OL = Low level output current during load transient
• I_OH = High level output current during load transient
• V_US = Target output voltage undershoot
• V_OS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR} = ΔV_{OUT_C} = 50 mV, and chose K_IND = 0.4. Equation 16 yields ESR no larger than 41.7 mΩ and Equation 17 yields C_OUT no smaller than 7.5 μF. For the target over/undershoot range of this design, V_US = V_OS = 5% × V_OUT = 250 mV. The C_OUT can be calculated to be no smaller than 108 μF and 28.5 μF by Equation 15 and Equation 17, respectively. Consider of derating, one 47-μF, 16-V and one 100-μF, 10-V ceramic capacitor with 5-mΩ ESR are used in parallel.