JAJSJN9 January   2021 LMR36015S

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 System Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Good Flag Output
      2. 9.3.2 Enable and Start-up
      3. 9.3.3 Current Limit and Short Circuit
      4. 9.3.4 Undervoltage Lockout and Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Auto Mode
      2. 9.4.2 Forced PWM Operation
      3. 9.4.3 Dropout
      4. 9.4.4 Minimum Switch On-Time
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Low Power 24-V, 1.5-A PFM Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH Tools
          2. 10.2.1.2.2  Choosing the Switching Frequency
          3. 10.2.1.2.3  Setting the Output Voltage
          4. 10.2.1.2.4  Inductor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  Input Capacitor Selection
          7. 10.2.1.2.7  CBOOT
          8. 10.2.1.2.8  VCC
          9. 10.2.1.2.9  CFF Selection
            1. 10.2.1.2.9.1 External UVLO
          10. 10.2.1.2.10 Maximum Ambient Temperature
      2. 10.2.2 Application Curves
      3. 10.2.3 Design 2: High Density 24-V, 1.5-A FPWM Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
    3. 10.3 What to Do and What Not to Do
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
10.2.1.2.5 Output Capacitor Selection

The value of the output capacitor and its ESR determine the output voltage ripple and load transient performance. The output capacitor bank is usually limited by the load transient requirements rather than the output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an upper bound on the ESR, required to meet a specified load transient.

Equation 6. GUID-7A385AD6-367A-4F49-A2C3-FF66BC13D64D-low.gif

where

  • ΔVOUT = output voltage transient
  • ΔIOUT = output current transient
  • K = ripple factor from Section 10.2.1.2.4

Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the output voltage ripple.

Equation 7. GUID-93718BDA-02C4-4144-9ECC-9BD00141AECC-low.gif

where

  • Vr = peak-to-peak output voltage ripple

The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple requirements.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.

Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.