JAJSKO0C October   2021  – November 2022 LMR51420

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed Frequency Peak Current Mode Control
      2. 8.3.2 Adjustable Output Voltage
      3. 8.3.3 Enable
      4. 8.3.4 Minimum On Time, Minimum Off Time, and Frequency Foldback
      5. 8.3.5 Bootstrap Voltage
      6. 8.3.6 Overcurrent and Short-Circuit Protection
      7. 8.3.7 Soft Start
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light-Load Operation (PFM Version)
      5. 8.4.5 Light-Load Operation (FPWM Version)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Voltage Set-Point
        3. 9.2.2.3 Switching Frequency
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Output Capacitor Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor
        8. 9.2.2.8 Undervoltage Lockout Set-Point
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Compact Layout for EMI Reduction
        2. 9.4.1.2 Feedback Resistors
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. Minimize the output capacitance to keep cost and size down. The output capacitor or capacitors, COUT, must be chosen with care because it directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 12. GUID-E72A2303-6933-4A2C-B8D0-02BF4186DAE2-low.gif

The other part is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 13. GUID-870935FC-3F79-4495-B48C-D3806F82123B-low.gif

The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than the sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rates. When a large load step occurs, output capacitors provide the required charge before the inductor current can slew to an appropriate level. The control loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new load level during this time. The output capacitance must be large enough to supply the current difference for eight clock cycles to maintain the output voltage within the specified range. Equation 14 shows the minimum output capacitance needed for a specified VOUT overshoot and undershoot.

Equation 14. GUID-E8DAB4CD-C81C-45CD-87EC-E1C33052E284-low.gif

where

  • KIND is the ripple ratio of the inductor current (ΔiL / IOUT).
  • IOL is the low level output current during load transient.
  • IOH is the high level output current during load transient.
  • VOUT_SHOOT is the target output voltage overshoot or undershoot.

For this design example, the target output ripple is 30 mV. Assuming ΔVOUT_ESR = ΔVOUT_C = 30 mV, choose KIND = 0.3. Equation 12 yields ESR no larger than 75 mΩ and Equation 13 yields COUT no smaller than 12 µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV. The COUT can be calculated to be no less than 32 µF by Equation 14. In summary, the most stringent criterion for the output capacitor is 44 µF. For this design, two 22-µF, 25-V, X7R ceramic capacitors with 5-mΩ ESR are used.