JAJSPD7 December   2022 LMR51440 , LMR51450

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2.     ESD Ratings
    3. 7.2 Recommended Operating Conditions
    4. 7.3 Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 System Characteristics
    7. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Peak Current Mode Control
      2. 8.3.2  Adjustable Output Voltage
      3. 8.3.3  Enable
      4. 8.3.4  Switching Frequency
      5. 8.3.5  Power-Good Flag Output
      6. 8.3.6  Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
      7. 8.3.7  Bootstrap Voltage
      8. 8.3.8  Overcurrent and Short-Circuit Protection
      9. 8.3.9  Soft Start
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light-Load Operation (PFM Version)
      5. 8.4.5 Light-Load Operation (FPWM Version)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Set-Point
        2. 9.2.2.2 Switching Frequency
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 Bootstrap Capacitor
        7. 9.2.2.7 Undervoltage Lockout Set-Point
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Compact Layout for EMI Reduction
        2. 9.5.1.2 Feedback Resistors
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Electrical Characteristics

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 4 V to 36 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
IQ-nonSW Operating quiescent current (non-switching) VEN = 3.3 V (PFM variant only) 25 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V, VIN = 24 V 3 6 µA
VIN_OPERATE VIN UVLO threshold VIN rising, Needed to start up 3.9 V
VIN falling, Once operating 3.4 V
ENABLE
VEN-H Enable input high level EN rising, Enable switching 1.1 1.25 1.4 V
VEN-L Enable input low level EN falling, Disable switching 0.8 1 1.12 V
ILKG-EN Enable input leakage current VEN = 3.3V 0.1 µA
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage TJ = 25°C 0.792 0.8 0.808 V
ILKG-FB Feedback leakage current FB = 1 V 100 nA
CURRENT LIMITS AND HICCUP
ISC High-side current limit(3) 5 A Version 6.4 8 9.6 A
ILS-LIMIT Low-side current limit(3) 5 A Version 5 A
ISC High-side current limit(3) 4 A Version 5.5 6.5 7.5 A
ILS-LIMIT Low-side current limit(3) 4 A Version 4 A
IL-ZC Zero cross detector threshold PFM variants only –0.1 A
IPEAK-MIN Minimum inductor peak current(3) 5 A Version, PFM variants only 1 A
IPEAK-MIN Minimum inductor peak current(3) 4 A Version, PFM variants only 0.8 A
IL-NEG Negative current limit(3) 5 A Version, FPWM variant only –2.5 A
IL-NEG Negative current limit(3) 4 A Version, FPWM variant only –1.7 A
VHICCUP Ratio of FB voltage to in-regulation FB voltage 40 %
POWER GOOD
VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 110 112 115 %
VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 88 90 92 %
VPG-HYS Power-Good hysteresis (rising & falling) % of FB voltage 2.0 %
VPG-VALID Minimum input voltage for proper Power-Good function 1.5 V
RPG Power-Good on-resistance VEN = 3.3 V 84 Ω
MOSFETS
RDS-ON-HS High-side MOSFET ON-resistance   78 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance   45 mΩ
VBOOT-SW-UVLO(R) BOOT-SW UVLO rising threshold VBOOT-SW rising 2.2 V
SWITCHING CHARACTERISTICS
FSW (CCM) Switching frequency RT = 31.6 kΩ 425 495 560 kHz
FSW (CCM) Switching frequency RT = Open or pull-up to voltage >1.0V 450 500 550 kHz
FSW (CCM) Switching frequency RT = 14.3 kΩ 1000 kHz
FSW (CCM) Switching frequency RT = Short to GND 1000 kHz
FSPREAD Spread of internal oscillator with Spread
Spectrum Enabled		 ±10 %
TIMING REQUIREMENT
tON-MIN Minimum switch on-time(2) VIN =24 V, Iout = 1 A 75 ns
tOFF-MIN Minimum switch off-time 135 ns
tON-MAX Maximum switch on-time 5 µs
tSS Internal soft-start time 3.2 5 7.2 ms
tw Short circuit wait time ("Hiccup" time) 96 ms
THERMAL SHUTDOWN
TSD-Rising(2) Thermal shutdown Shutdown threshold 160 ℃
TSD-Falling(2) Thermal shutdown Recovery threshold 140 ℃
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Not production tested. Specified by correlation by design.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.