JAJSSS0 August   2024 LMR51606-Q1 , LMR51610-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency Peak Current Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable
      4. 7.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback
      5. 7.3.5 Bootstrap Voltage
      6. 7.3.6 Overcurrent and Short-Circuit Protection
      7. 7.3.7 Soft Start
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation (PFM Version)
      5. 7.4.5 Light-Load Operation (FPWM Version)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor
        8. 8.2.2.8 Undervoltage Lockout Setpoint
        9. 8.2.2.9 Replacing Non Sync Buck Converter
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 Overcurrent and Short-Circuit Protection

The LMR516xx-Q1 incorporates both peak and valley inductor current limit to provide protection to the device from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for sustained short circuits.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. See the Functional Block Diagram for more details. The peak current of high-side switch is limited by a clamped maximum peak current threshold IHS_PK(OC) (see Electrical Characteristics), which is constant.

The current going through the low-side MOSFET is also sensed and monitored. When the low-side switch turns on, the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching cycle if the current is above the low-side current limit, ILS_V(OC) (see Electrical Characteristics). The low-side switch is kept ON so that inductor current keeps ramping down until the inductor current ramps below ILS_V(OC). Then, the low-side switch is turned OFF and the high-side switch is turned on after a dead time. After ILS_V(OC) is achieved, peak and valley current limit controls the maximum current delivered and can be calculated using Equation 6.

Equation 6. IOUT_MAX=IHS_PK(OC)+ILS_V(OC)2

If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers IHS_PK(OC) for 256 consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts down and keeps off for a period of hiccup, THICCUP (150ms typical) before the LMR516xx-Q1 tries to start again. If overcurrent or a short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, preventing overheating and potential damage to the device.

For the FPWM version, the inductor current is allowed to go negative. When this current exceeds the low-side negative current limit, ILS(NOC), the low-side switch is turned off and high-side switch is turned on immediately. This event is used to protect the low-side switch from excessive negative current.