JAJSPN0A August   2024  – November 2024 LMR51635

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency Peak Current Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable
      4. 7.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback
      5. 7.3.5 Bootstrap Voltage
      6. 7.3.6 Overcurrent and Short-Circuit Protection
      7. 7.3.7 Soft Start
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation (PFM Version)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Set-Point
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor
        8. 8.2.2.8 Undervoltage Lockout Set-Point
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Minimum ON Time, Minimum OFF Time, and Frequency Foldback

The minimum ON time (tON-MIN) is the shortest duration of time that the high-side switch can be turned on. tON-MIN is typically 70ns for the LMR51635. The minimum OFF time (tOFF-MIN) is the shortest duration of time that the high-side switch can be off. tOFF-MIN is typically 200ns. In CCM operation, tON-MIN and tOFF-MIN limit the voltage conversion range without switching frequency foldback.

The minimum duty cycle without frequency foldback allowed is:

Equation 2. DMIN=tON_MIN×fSW

The maximum duty cycle without frequency foldback allowed is:

Equation 3. DMAX=1-tOFF_MIN×fSW

Given a required output voltage, the maximum VIN without frequency foldback can be found by:

Equation 4. VIN_MAX=VOUTfSW×tON_MIN

The minimum VIN without frequency foldback can be calculated by:

Equation 5. VIN_MIN=VOUT1-fSW×tOFF_MIN

In the LMR51635, a frequency foldback scheme is employed once the tON-MIN or tOFF-MIN is triggered, which can extend the maximum duty cycle or lower the minimum duty cycle.

The on time decreases while VIN voltage increases. Once the on time decreases to tON-MIN, the switching frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in regulation according to Equation 2.

The frequency foldback scheme also works after larger duty cycle is needed under a low VIN condition. The frequency decreases after the device hits the tOFF-MIN, which extends the maximum duty cycle according to Equation 3. In such condition, the frequency can be as low as approximately 190kHz. A wide range of frequency foldback allows for the LMR51635 output voltage to stay in regulation with a much lower supply voltage VIN, which leads to a lower effective dropout.

With frequency foldback while maintaining a regulated output voltage, VIN_MAX is raised and VIN_MIN is lowered by decreased fSW.