JAJSB34I January   2011  – August 2021 LMZ14201H

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 COT Control Circuit Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Overvoltage Comparator
      2. 7.3.2 Current Limit
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Zero Coil Current Detection
      5. 7.3.5 Prebiased Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Discontinuous Conduction and Continuous Conduction Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Steps for the LMZ14201H Application
          1. 8.2.2.1.1 Enable Divider, RENT and RENB Selection
          2. 8.2.2.1.2 Output Voltage Selection
          3. 8.2.2.1.3 Soft-Start Capacitor, CSS, Selection
          4. 8.2.2.1.4 Output Capacitor, CO, Selection
            1. 8.2.2.1.4.1 Capacitance
            2. 8.2.2.1.4.2 ESR
          5. 8.2.2.1.5 Input Capacitor, CIN, Selection
          6. 8.2.2.1.6 ON-Time, RON, Resistor Selection
            1. 8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Module SMT Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Power Dissipation and Board Thermal Requirements
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.2.1.4.2 ESR

The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the overvoltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT peak-to-peak ripple voltage and to avoid overvoltage protection during normal operation. The following equations can be used:

Equation 7. ESRMAX-RIPPLE ≤ VOUT-RIPPLE / ILR P-P

where

Equation 8. ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P × AFB )

where

  • AFB is the gain of the feedback network from VOUT to VFB at the switching frequency.

As worst-case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1.

The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the output capacitor is:

Equation 9. I(COUT(RMS)) = ILR P-P / √12