JAJSG07E August   2012  – August 2018 LMZ21701

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VIN = 12Vでの効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Package Construction
    4. 7.4 Feature Description
      1. 7.4.1 Input Undervoltage Lockout
      2. 7.4.2 Enable Input (EN)
      3. 7.4.3 Soft Start and Tracking Function (SS)
      4. 7.4.4 Power Good Function (PG)
      5. 7.4.5 Output Voltage Setting
      6. 7.4.6 Output Current Limit and Output Short Circuit Protection
      7. 7.4.7 Thermal Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 PWM Mode Operation
      2. 7.5.2 PSM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Input Capacitor (CIN)
        3. 8.2.2.3 Output Capacitor (COUT)
        4. 8.2.2.4 Soft-start Capacitor (CSS)
        5. 8.2.2.5 Power Good Resistor (RPG)
        6. 8.2.2.6 Feedback Resistors (RFBB and RFBT)
      3. 8.2.3 Application Curves
        1. 8.2.3.1 VOUT = 1.2 V
        2. 8.2.3.2 VOUT = 1.8 V
        3. 8.2.3.3 VOUT = 2.5 V
        4. 8.2.3.4 VOUT = 3.3 V
        5. 8.2.3.5 VOUT = 5.0 V
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
    1. 9.1 Voltage Range
    2. 9.2 Current Capability
    3. 9.3 Input Connection
      1. 9.3.1 Voltage Drops
      2. 9.3.2 Stability
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Minimize the High di/dt Loop Area
      2. 10.1.2 Protect the Sensitive Nodes in the Circuit
      3. 10.1.3 Provide Thermal Path and Shielding
    2. 10.2 Layout Example
      1. 10.2.1 High Density Layout Example for Space Constrained Applications
        1. 10.2.1.1 35 mm² Solution Size (Single Sided)
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIL|8
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics(1)

Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS
IQ Operating quiescent current EN = high, IOUT = 0 mA, TJ = -40°C to 85°C
device not switching		 17 25 μA
EN = high, IOUT = 0 mA, TJ = -40°C to 125°C
device not switching		 17 28 μA
ISD Shutdown current EN = low, TJ = -40°C to 85°C 1.5 4 μA
EN = low, TJ = -40°C to 125°C 1.5 5 μA
VINUVLO Input under voltage lock out rising threshold 2.8 2.9 3 V
VINUVLO-HYS Input under voltage lock out hysteresis 0.125 0.18 0.26 V
TSD Thermal shutdown Rising Threshold 160 °C
TSD-HYST Thermal shutdown hysteresis 30 °C
CONTROL
VIH, ENABLE Enable logic HIGH voltage 0.9 V
VIL, ENABLE Enable logic LOW voltage 0.3 V
ILKG Input leakage current EN = VIN or GND 0.01 1 μA
VTH_PG Power Good threshold voltage Rising (% VOUT) 92% 95% 98%
Falling (% VOUT) 87% 90% 93%
VOL_PG Power Good output low voltage IPG = -2 mA 0.07 0.3 V
ILKG_PG Power Good leakage current VPG = 1.8 V 1 400 nA
ISS Softstart Pin source current 2.5 2.84 3.2 μA
POWER STAGE
RDS(ON) High-Side MOSFET ON Resistance VIN ≥ 6 V 82 mΩ
VIN = 3 V 120
Low-Side MOSFET ON Resistance VIN ≥ 6 V 40 mΩ
VIN = 3 V 50
L Integrated power inductor value 2.2 μH
DCR Integrated power inductor DC resistance 92 mΩ
ICL-HS High-Side MOSFET Current Limit TA = 25°C 1.4 1.8 2.2 A
ICL-LS Low-Side MOSFET Current Limit TA = 25°C 1.2 A
ICL-DC Output (DC) current limit VOUT = 5 V, TA = 85°C 1.3 A
OUTPUT
VREF Internal reference voltage 0.7869 0.803 0.8191 V
IFB Feedback pin leakage current VFB = 0.8 V 1 100 nA
VOUT Light load initial voltage accuracy Power save mode, COUT = 22 µF, TA = -40°C to 85°C, 1% FB Resistors -2.3% 2.8%
VOUT Load regulation VOUT = 3.3 V
PWM mode operation		 0.05% / A
VOUT Line regulation 3 V ≤ VIN ≤ 17 V, VOUT= 3.3 V, IOUT = 1000 mA
PWM mode operation		 0.02% / V
SYSTEM CHARACTERISTICS
η Full Load Efficiency VOUT = 3.3 V, IOUT = 1000 mA 93%
Light Load Efficiency VOUT = 3.3 V, IOUT = 1 mA 72%
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.