JAJSBZ7E JULY   2013  – December 2019 LMZ31710

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = VIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = VIN = 5 V)
    8. 6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and PVIN Input Voltage
      2. 7.3.2  3.3-V PVIN Operation
      3. 7.3.3  Adjusting the Output Voltage (0.6 V to 5.5 V)
      4. 7.3.4  Capacitor Recommendations For the LMZ31710 Power Supply
        1. 7.3.4.1 Capacitor Technologies
          1. 7.3.4.1.1 Electrolytic, Polymer-Electrolytic Capacitors
          2. 7.3.4.1.2 Ceramic Capacitors
          3. 7.3.4.1.3 Tantalum, Polymer-Tantalum Capacitors
        2. 7.3.4.2 Input Capacitor
        3. 7.3.4.3 Output Capacitor
      5. 7.3.5  Transient Response
        1. 7.3.5.1 Transient Response Waveforms
      6. 7.3.6  Power Good (PWRGD)
      7. 7.3.7  Light Load Efficiency (LLE)
      8. 7.3.8  SYNC_OUT
      9. 7.3.9  Parallel Operation
      10. 7.3.10 Power-Up Characteristics
      11. 7.3.11 Pre-Biased Start-Up
      12. 7.3.12 Remote Sense
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Output On/Off Inhibit (INH)
      15. 7.3.15 Slow Start (SS/TR)
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Synchronization (CLK)
      18. 7.3.18 Sequencing (SS/TR)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programmable Undervoltage Lockout (UVLO)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 Input Capacitance
        5. 8.2.2.5 Output Capacitance
    3. 8.3 Additional Application Schematics
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Considerations
    2. 10.2 Layout Examples
      1. 10.2.1 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,
CIN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, COUT = 4 × 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT Output current TA = 85°C, natural convection 0(1) 10 A
VIN Input bias voltage range Over output current range 4.5 17 V
PVIN Input switching voltage range Over output current range 2.95(3) 17(4) V
UVLO VIN undervoltage lockout VIN Increasing 4 4.5 V
VIN Decreasing 3.5 3.85
VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5(5) V
VOUT Set-point voltage tolerance TA = 25°C, IOUT = 0 A ±1%(2)
Temperature variation –40°C ≤ TA ≤ +85°C, IOUT = 0 A ±0.2%
Line regulation Over input voltage range ±0.1%
Load regulation Over output current range ±0.2%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5%(2)
η Efficiency PVIN = VIN = 12 V
IO = 5 A  		 VOUT = 5 V, fSW = 1 MHz 93%
VOUT = 3.3 V, fSW = 750 kHz 92%
VOUT = 2.5 V, fSW = 750 kHz 90%
VOUT = 1.8 V, fSW = 500 kHz 89%
VOUT = 1.2 V, fSW = 300 kHz 86%
VOUT = 0.9 V, fSW = 250 kHz 84%
VOUT = 0.6 V, fSW = 200 kHz 81%
PVIN = VIN = 5 V
IO = 5 A  		 VOUT = 3.3 V, fSW = 750 kHz 94%
VOUT = 2.5 V, fSW = 750 kHz 93%
VOUT = 1.8 V, fSW = 500 kHz 92%
VOUT = 1.2 V, fSW = 300 kHz 89%
VOUT = 0.9 V, fSW = 250 kHz 87%
VOUT = 0.6 V, fSW = 200 kHz 83%
Output voltage ripple 20 MHz bandwidth 14 mVP-P
ILIM Current limit threshold ILIM pin open 15 A
ILIM pin to AGND 12 A
Transient response 1 A/µs load step from
25 to 75% IOUT(max) 		 Recovery time 100 µs
VOUT over/undershoot 80 mV
VINH Inhibit threshold voltage Inhibit High Voltage 1.3 open(6) V
Inhibit Low Voltage –0.3 1.1
IINH INH Input current VINH < 1.1 V -1.15 μA
INH Hysteresis current VINH > 1.3 V -3.3 μA
II(stby) Input standby current INH pin to AGND 2 10 µA
Power Good PWRGD Thresholds VOUT rising Good 95%
Fault 108%
VOUT falling Fault 91%
Good 104%
PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V
ƒSW Switching frequency RRT = 169 kΩ 400 500 600 kHz
ƒCLK Synchronization frequency CLK Control 200 1200 kHz
VCLK-H CLK High-Level 2 5.5 V
VCLK-L CLK Low-Level 0.5 V
DCLK CLK Duty Cycle 20% 50% 80%
Thermal Shutdown Thermal shutdown 175 °C
Thermal shutdown hysteresis 10 °C
CIN External input capacitance Ceramic 44(7) µF
Non-ceramic 100(7)
COUT External output capacitance VOUT = 0.6 V to 5.5 V Ceramic 47(8) 200 1500 µF
VOUT = 0.6 V to 5.5 V Non-ceramic 220(8) 5000(9)
Equivalent series resistance (ESR) 35 mΩ
(1) See Light Load Efficiency (LLE) for more information for output voltages < 1.5 V.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
(3) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See Table 7 for more details.
(4) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See Table 7 for more details.
(5) The maximum output voltage may be limited by the power dissipation. The maximum power dissipation of this device is 4.5 W.
(6) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pullup. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.
(7) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.
(8) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance must include at least 1 × 47 µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.
(9) The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors. It may be necessary to increase the slow-start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on adjusting the slow-start time.