JAJSBZ7E JULY   2013  – December 2019 LMZ31710

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = VIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = VIN = 5 V)
    8. 6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and PVIN Input Voltage
      2. 7.3.2  3.3-V PVIN Operation
      3. 7.3.3  Adjusting the Output Voltage (0.6 V to 5.5 V)
      4. 7.3.4  Capacitor Recommendations For the LMZ31710 Power Supply
        1. 7.3.4.1 Capacitor Technologies
          1. 7.3.4.1.1 Electrolytic, Polymer-Electrolytic Capacitors
          2. 7.3.4.1.2 Ceramic Capacitors
          3. 7.3.4.1.3 Tantalum, Polymer-Tantalum Capacitors
        2. 7.3.4.2 Input Capacitor
        3. 7.3.4.3 Output Capacitor
      5. 7.3.5  Transient Response
        1. 7.3.5.1 Transient Response Waveforms
      6. 7.3.6  Power Good (PWRGD)
      7. 7.3.7  Light Load Efficiency (LLE)
      8. 7.3.8  SYNC_OUT
      9. 7.3.9  Parallel Operation
      10. 7.3.10 Power-Up Characteristics
      11. 7.3.11 Pre-Biased Start-Up
      12. 7.3.12 Remote Sense
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Output On/Off Inhibit (INH)
      15. 7.3.15 Slow Start (SS/TR)
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Synchronization (CLK)
      18. 7.3.18 Sequencing (SS/TR)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programmable Undervoltage Lockout (UVLO)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 Input Capacitance
        5. 8.2.2.5 Output Capacitance
    3. 8.3 Additional Application Schematics
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Considerations
    2. 10.2 Layout Examples
      1. 10.2.1 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

LMZ31710 Frontpage photo.png
RVQ Package
42-Pin B3QFN
(Top View)
LMZ31710 pinout_rvq_42_pinnames OCP.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND 2 - Zero volt reference for the analog control circuit. These pins are not connected together internal to the device and must be connected to one another using an AGND plane of the PCB. These pins are associated with the internal analog ground (AGND) of the device. Keep AGND separate from PGND, as a single connection is made internal to the device. See Layout.
23
PGND 20 - This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with PVIN and VOUT. Keep PGND separate from AGND, as a single connection is made internal to the device.
21
31
32
33
VIN 3 I Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias supply. Connect bypass capacitors between this pin and PGND.
PVIN 1 I Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the input supply. Connect bypass capacitors between these pins and PGND.
11
12
39
40
VOUT 34 O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND.
35
36
37
38
41
PH 10 O Phase switch node. These pins must be connected to one another using a small copper island under the device for thermal relief. Do not place any external component on these pins or tie them to a pin of another function.
13
14
15
16
17
18
19
42
DNC 5 - Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
9
24
ISHARE 25 O Current share pin. Connect this pin to other LMZ31710 device's ISHARE pin when paralleling multiple LMZ31710 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from all other signals or ground.
OCP_SEL 4 I Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to AGND for cycle-by-cycle operation. See Overcurrent Protection for more details.
ILIM 6 I Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the current limit threshold by approximately 3 A.
SYNC_OUT 7 O Synchronization output pin. Provides a 180° out-of-phase clock signal.
PWRGD 8 O Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately ±6% out of regulation. A pull-up resistor is required.
RT/CLK 22 I This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be used to synchronize to an external clock.
VADJ 26 I Connecting a resistor between this pin and AGND sets the output voltage.
SENSE+ 27 O Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect this pin to VOUT at the load for improved regulation.
SS/TR 28 I Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time. A voltage applied to this pin allows for tracking and sequencing control.
STSEL 29 I Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the TR feature.
INH/UVLO 30 I Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO voltage.