JAJSER6C February   2018  – March 2023 LMZM23600

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Scheme
      2. 8.3.2 Soft-Start Function
      3. 8.3.3 Enable and External UVLO Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Power Good (PGOOD) Function
      7. 8.3.7 MODE/SYNC Function
        1. 8.3.7.1 Forced PWM Mode
        2. 8.3.7.2 Auto PFM Mode
        3. 8.3.7.3 Dropout Mode
        4. 8.3.7.4 SYNC Operation
      8. 8.3.8 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
      2. 8.4.2 FPWM Operation
      3. 8.4.3 Auto PFM Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Maximum Input Voltage for VOUT < 2.5 V
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Input Capacitor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Feedback Voltage Divider for Adjustable Output Voltage Versions
        5. 9.2.2.5 RPU - PGOOD Pullup Resistor
        6. 9.2.2.6 VIN Divider and Enable
      3. 9.2.3 Application Curves
        1. 9.2.3.1 VOUT = 5 V
        2. 9.2.3.2 VOUT = 3.3 V
        3. 9.2.3.3 VOUT = 12 V
        4. 9.2.3.4 VOUT = 15 V
        5. 9.2.3.5 VOUT = 2.5 V
        6. 9.2.3.6 VOUT = 1.2 V and VOUT = 1.8 V
        7. 9.2.3.7 VOUT = 5 V and 3.3 V Fixed Output Options
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Voltage Range
      2. 9.4.2 Supply Current Capability
      3. 9.4.3 Supply Input Connections
        1. 9.4.3.1 Voltage Drops
        2. 9.4.3.2 Stability
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Thermal Design
      2. 9.5.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
FEEDBACK
VFBInitial output voltage accuracy (3.3-V and 5-V fixed output)VIN = 4 V to 36 V, open loop–1.5%1.5%
VFBReference voltage (ADJ option)VIN = 4 V to 36 V, open loop0.98511.015V
IFBInput current from FB to GND (ADJ option)FB = 1 V20nA
CURRENT
IQOperating quiescent current; measured at VIN pinVIN = 12 V, VFB = +10%, VOUT = 5 V7µA
VIN = 12 V, VFB =  +10%, VOUT = 5 V, TJ = 85°C16µA
VIN = 12 V, VFB =  +10%, VOUT = 5 V, TJ = 125°C18
VIN = 24 V, VFB =  +10%, VOUT = 5 V12
VIN = 24 V, VFB =  +10%, VOUT = 5 V, TJ = 85°C24
VIN = 24 V, VFB =  +10%, VOUT = 5 V, TJ = 125°C26
IBBias current into the VOUT pinVIN = 24 V, VFB =  +10%, VOUT = 5 V, Mode = 0 V4880µA
ISDShutdown quiescent current; measured at VIN pinEN = 0 V, VIN = 12 V, TJ = 25°C1.8µA
EN = 0 V, VIN = 12 V, TJ = 85°C3
EN = 0 V, VIN = 24 V, TJ = 25°C5
EN = 0 V, VIN = 24 V, TJ = 85°C10
UNDERVOLTAGE LOCKOUT (UVLO)
VIN_UVLOMinimum input voltage to operateRising3.13.53.85V
VIN_UVLO_HYSTUVLO hysteresis0.20.250.3V
POWER GOOD FLAG (PGOOD)
VPGOOD_OVPGOOD upper threshold voltageRising, % of Vout103.5%106.7%109%
VPGOOD_UVPGOOD lower threshold voltageFalling, % of Vout92%94.7%97%
VPGOOD_GUARDMagnitude of PGOOD lower threshold difference from steady state output voltage.Steady state output voltage PGOOD threshold read at the same TJ  and VIN4%
VPGOOD_HYSTPGOOD hysteresis as a percent of output voltage set point1.4%
VPGOOD_VALIDMinimum input voltage for proper PGOOD function50-µA pullup to PGOOD pin, EN = 0 V, TJ = 25°C1.01.5V
tRESET_FILTERGlitch filter time constant for PGOOD function190µs
VOLLow-level PGOOD function output voltage50-µA pullup to PGOOD pin, VIN = 1.5 V, EN = 0 V0.4V
0.5-mA pullup to PGOOD pin, VIN = 12 V, EN = 0 V0.4
1-mA pullup to PGOOD pin, VIN = 12 V, EN = 3.3 V0.4
RPGOOD_RDSONRDSON of the PGOOD output pull down50110Ω
SWITCHING FREQUENCY
fSWSwitching frequencyVIN = 24 V, 5-V and 3.3-V fixed output options675750825kHz
VIN = 24 V, ADJ output options89010001090
VIN = 36 V, 5-V and 3.3-V fixed output options750
VIN = 36 V, ADJ output options800
FREQUENCY SYNCHRONIZATION AND MODE
fSYNCSync frequency range5-V and 3.3-V fixed output options VOUT + VDROPOUT < VIN < 36 V500825kHz
ADJ output options VOUT + VDROPOUT< VIN < 28 V7001100
DSYNCSync input duty cycle range2.3 V < HIGH state input < 5.5 V25%75%
VMODE_HIGHMODE/SYNC input logic HIGH voltage to enter FPWM mode1.5V
VMODE_LOWMODE/SYNC input logic LOW voltage to enter AUTO PFM mode0.4V
IMODEMODE/SYNC leakage currentVIN = 12 V, VMODE/SYNC = 3.3 V1µA
VIN = 12 V, VMODE/SYNC = 12V5
tMODEMODE transition time to FPWMVIN = 12 V, VOUT = 5 V, IOUT= 20 mA300µs
MODE transition time to AUTO PFMVIN = 12 V, VOUT = 5 V, IOUT = 20 mA300
CURRENT LIMIT PROTECTION
IL-HS0.5-A option high-side switch current limitDuty cycle approaches 0%0.941.351.6A
IL-LS0.5-A option low-side switch current limit0.50.6250.75A
IL-ZCZero-cross current limitMODE/SYNC = logic LOW–0.01A
IL-NEGLow-side reverse current limit (positive current ino the SW pin to GND)MODE/SYNC = logic HIGH0.50.8A
POWER STAGE CHARACTERISTICS
HS RDS-ONHigh-side MOSFET on-resistance220mΩ
LS RDS-ONLow-side MOSFET on-resistance200mΩ
tON-MINMinimum high-side on-timeIOUT = 500 mA5080ns
tOFF-MINMinimum high-side off-timeIOUT = 500 mA, ADJ62100ns
DMAXMaximum switch duty cycle5-V and 3.3-V fixed output options93%
ADJ option91%
While in frequency foldback97%
LIntegrated inductor - inductance10µH
LDCRIntegrated inductor - DCR390mΩ
ENABLE
VENEnable input threshold voltageRising1.71.92V
VEN_HYSTEnable input threshold hysteresis0.420.52V
VEN_WAKEEnable input wake-up threshold0.4V
IENEnable pin input currentVIN = VEN = 12 V2.7µA
VCC REGULATOR
VCCInternal VCC voltageVIN = 12 V, VOUT < 3.3 V3.05V
VIN = 12 V, VOUT ≥ 3.3V3.15
VCC_UVLOInternal VCC voltage input UVLOVIN rising2.232.733.25V
VCC_UVLO_HYSTInternal VCC voltage input UVLO hysteresisHysteresis below VCC_UVLO150240mV
SOFT START
tSSSoft-start timeTime for VREF to ramp from 0% to 90%1.83.55.5ms
tEN_LVTurnon delay with low VINVIN < 4.2 V4ms
tENTurnon delayVIN = 12 V0.7ms
tWShort circuit wait time (hiccup time)8.0ms
THERMAL PROTECTION
TSDThermal shutdownRising threshold155°C
TSD_HYSTThermal shutdown hysteresis15°C